Datasheet > CY2309ESXI-1HT

CY2309ESXI-1HT

更新时间： 2023-07-15 00:00:00

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		光电二极管
页数	文件大小	规格书
17页	383K
描述
PLL Based Clock Driver, 2309 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 0.150 INCH, LEAD FREE, MS-012, SOIC-16

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CY2309ESXI-1HT 数据手册

CY2305

CY2309

REF. Input to CLKA/CLKB Delay vs. Loading Difference between CLKOUT and CLKA/CLKB

Pins

Zero Delay and Skew Control

All outputs must be uniformly loaded to achieve Zero Delay between the input and output. Since the CLKOUT pin is the internal

feedback to the PLL, its relative loading can adjust the input-output delay. This is shown in the above graph.

For applications requiring zero input-output delay, all outputs, including CLKOUT, must be equally loaded. Even if CLKOUT is not

used, it must have a capacitive load, equal to that on other outputs, for obtaining zero input-output delay. If input to output delay

adjustments are required, use the above graph to calculate loading differences between the CLKOUT pin and other outputs.

For zero output-output skew, be sure to load all outputs equally. For further information refer to the application note entitled “CY2305

and CY2309 as PCI and SDRAM Buffers.”

Document #: 38-07140 Rev. *H

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型号	品牌	获取价格	描述	数据表
CY2309EZXC-1HT	CYPRESS	获取价格	PLL Based Clock Driver, 2309 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16,
CY2309EZXI-1H	CYPRESS	获取价格	PLL Based Clock Driver, 2309 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16,
CY2309EZXI-1HT	CYPRESS	获取价格	PLL Based Clock Driver, 2309 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16,
CY2309NZ	CYPRESS	获取价格	Nine-Output 3.3V Buffer
CY2309NZ_08	CYPRESS	获取价格	Nine-Output 3.3V Buffer
CY2309NZSC-1H	CYPRESS	获取价格	Nine-Output 3.3V Buffer
CY2309NZSC-1HT	CYPRESS	获取价格	Nine-Output 3.3V Buffer
CY2309NZSI-1H	CYPRESS	获取价格	Nine-Output 3.3V Buffer
CY2309NZSXC-1H	CYPRESS	获取价格	Nine-Output 3.3V Buffer
CY2309NZSXC-1H	INFINEON	获取价格	3.3V Non Zero Delay Buffer