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CY22050_09

更新时间: 2024-11-23 06:51:31
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟发生器闪存
页数 文件大小 规格书
10页 271K
描述
One-PLL General Purpose Flash Programmable Clock Generator

CY22050_09 数据手册

 浏览型号CY22050_09的Datasheet PDF文件第2页浏览型号CY22050_09的Datasheet PDF文件第3页浏览型号CY22050_09的Datasheet PDF文件第4页浏览型号CY22050_09的Datasheet PDF文件第5页浏览型号CY22050_09的Datasheet PDF文件第6页浏览型号CY22050_09的Datasheet PDF文件第7页 
CY22050,  
CY220501  
One-PLL General Purpose  
Flash Programmable Clock Generator  
Features  
Benefits  
Integrated phase-locked loop (PLL)  
Commercial and Industrial operation  
Flash-programmable  
Internal PLL to generate six outputs up to 200 MHz. Able to  
generate custom frequencies from an external reference  
crystal or driven source.  
Performance guaranteed for applications that require an  
extended temperature range.  
Field-programmable  
Reprogrammabletechnologyallowseasycustomization, quick  
turnaround on design changes and product performance  
enhancements, and better inventory control. Parts can be  
reprogrammed up to 100 times, reducing inventory of custom  
parts and providing an easy method for upgrading existing  
Low-skew, low-jitter, high-accuracy outputs  
3.3V operation with 2.5V output option  
16-Pin TSSOP package (CY22050)  
16-Pin TSSOP package with NiPdAu lead finish (CY220501)  
designs.  
In-house programming of samples and prototype quantities is  
available using the CY3672 FTG Development Kit. Production  
quantities are available through Cypress’s value-added distri-  
bution partners or by using third party programmers from BP  
Microsystems, HiLo Systems, and others.  
Industry standard packaging saves on board space.  
Table 1. Device Selection  
Part Number  
Outputs  
Input Frequency Range  
Output Frequency Range  
Specifications  
CY22050KFZXC  
6
8 MHz–30 MHz (external crystal)  
1 MHz–133 MHz (driven clock)  
80 kHz–200 MHz (3.3V)  
80 KHz–166.6 MHz (2.5V)  
Field-programmable  
commercial temperature  
CY22050KFZXI  
CY220501KFZXI  
6
6
8 MHz–30 MHz (external crystal)  
1 MHz–133 MHz (driven clock)  
80 kHz–166.6 MHz (3.3V)  
80 KHz–150 MHz (2.5V)  
Field-programmable  
industrial temperature  
8 MHz–30 MHz (external crystal)  
1 MHz–133 MHz (driven clock)  
80 kHz–166.6 MHz (3.3V)  
80 KHz–150 MHz (2.5V)  
Field-programmable  
industrial temperature  
NiPdAu lead finish  
Logic Block Diagram  
LCLK1  
LCLK2  
Divider  
Bank 1  
Output  
Select  
Matrix  
LCLK3  
LCLK4  
XIN  
Q
OSC.  
Φ
XOUT  
VCO  
PLL  
P
Divider  
Bank 2  
CLK5  
CLK6  
OE  
AVSS VSS  
VDD  
AVDD  
VDDL VSSL PWRDWN  
Cypress Semiconductor Corporation  
Document #: 38-07006 Rev. *G  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised July 24, 2009  
[+] Feedback  

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