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CY220501KFZXC PDF预览

CY220501KFZXC

更新时间: 2024-11-26 19:02:39
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
11页 408K
描述
Clock Generator, 200MHz, CMOS, PDSO16, 4.40 MM, LEAD FREE, MO-153, TSSOP-16

CY220501KFZXC 技术参数

是否Rohs认证: 符合生命周期:Active
零件包装代码:TSSOP包装说明:TSSOP,
针数:16Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.78其他特性:CAN ALSO OPERATE AT 2.5V SUPPLY
JESD-30 代码:R-PDSO-G16JESD-609代码:e3
长度:5 mm湿度敏感等级:3
端子数量:16最高工作温度:70 °C
最低工作温度:最大输出时钟频率:200 MHz
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260主时钟/晶体标称频率:133 MHz
座面最大高度:1.1 mm最大供电电压:3.465 V
最小供电电压:3.135 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:MATTE TIN
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:20
宽度:4.4 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHER
Base Number Matches:1

CY220501KFZXC 数据手册

 浏览型号CY220501KFZXC的Datasheet PDF文件第2页浏览型号CY220501KFZXC的Datasheet PDF文件第3页浏览型号CY220501KFZXC的Datasheet PDF文件第4页浏览型号CY220501KFZXC的Datasheet PDF文件第5页浏览型号CY220501KFZXC的Datasheet PDF文件第6页浏览型号CY220501KFZXC的Datasheet PDF文件第7页 
CY22050,  
CY220501  
One-PLL General-Purpose  
Flash-Programmable Clock Generator  
— 80 kHz–200 MHz (3.3 V)  
Features  
— 80 KHz–166.6 MHz (2.5 V)  
Industrial temperature  
Integrated phase-locked loop (PLL)  
Commercial and Industrial operation  
Flash-programmable  
— 80 kHz–166.6 MHz (3.3 V)  
— 80 KHz–150 MHz (2.5 V)  
Field-programmable  
Functional Description  
Low-skew, low-jitter, high-accuracy outputs  
3.3 V operation with 2.5 V output option  
16-pin TSSOP package (CY22050)  
16-pin TSSOP package with NiPdAu lead finish (CY220501)  
The CY22050 is programmable clock generator for use in  
networking,  
telecommunication,  
datacom,  
and  
other  
general-purpose applications. The CY22050 offers up to six  
configurable outputs in a 16-pin TSSOP, running off a 3.3 V  
power supply. The on-chip reference oscillator is designed to run  
off an 8–30-MHz crystal, or a 1–133-MHz external clock signal.  
Input freqency range:  
The CY22050 has a single PLL driving 6 programmable output  
clocks. The output clocks are derived from the PLL or the  
reference frequency (REF). Output post dividers are available for  
either. Four of the outputs can be set as 3.3 V or 2.5 V, for use  
in a wide variety of portable and low-power applications.  
— 8 MHz–30 MHz (external crystal)  
— 1 MHz–133 MHz (driven clock)  
Output freqency range:  
Commercial temperature  
The CY220501 is the CY22050 with NiPdAu lead finish.  
Logic Block Diagram  
LCLK1  
Divider  
Bank 1  
LCLK2  
Output  
Select  
Matrix  
LCLK3  
LCLK4  
XIN  
Q
OSC.  
VCO  
PLL  
XOUT  
P
Divider  
Bank 2  
CLK5  
CLK6  
OE  
AVSS VSS  
VDD  
AVDD  
VDDL VSSL PWRDWN  
Cypress Semiconductor Corporation  
Document #: 38-07006 Rev. *J  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised March 30, 2011  
[+] Feedback  

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