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CY22050_11 PDF预览

CY22050_11

更新时间: 2024-11-23 09:41:11
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟发生器闪存
页数 文件大小 规格书
11页 303K
描述
One-PLL General-Purpose Flash-Programmable Clock Generator

CY22050_11 数据手册

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CY22050,  
CY220501  
One-PLL General-Purpose  
Flash-Programmable Clock Generator  
— 80 kHz–200 MHz (3.3 V)  
Features  
— 80 KHz–166.6 MHz (2.5 V)  
Industrial temperature  
Integrated phase-locked loop (PLL)  
Commercial and Industrial operation  
Flash-programmable  
— 80 kHz–166.6 MHz (3.3 V)  
— 80 KHz–150 MHz (2.5 V)  
Field-programmable  
Functional Description  
Low-skew, low-jitter, high-accuracy outputs  
3.3 V operation with 2.5 V output option  
16-pin TSSOP package (CY22050)  
16-pin TSSOP package with NiPdAu lead finish (CY220501)  
The CY22050 is programmable clock generator for use in  
networking,  
telecommunication,  
datacom,  
and  
other  
general-purpose applications. The CY22050 offers up to six  
configurable outputs in a 16-pin TSSOP, running off a 3.3 V  
power supply. The on-chip reference oscillator is designed to run  
off an 8–30-MHz crystal, or a 1–133-MHz external clock signal.  
Input freqency range:  
The CY22050 has a single PLL driving 6 programmable output  
clocks. The output clocks are derived from the PLL or the  
reference frequency (REF). Output post dividers are available for  
either. Four of the outputs can be set as 3.3 V or 2.5 V, for use  
in a wide variety of portable and low-power applications.  
— 8 MHz–30 MHz (external crystal)  
— 1 MHz–133 MHz (driven clock)  
Output freqency range:  
Commercial temperature  
The CY220501 is the CY22050 with NiPdAu lead finish.  
Logic Block Diagram  
LCLK1  
Divider  
Bank 1  
LCLK2  
Output  
Select  
Matrix  
LCLK3  
LCLK4  
XIN  
Q
OSC.  
Φ
VCO  
PLL  
XOUT  
P
Divider  
Bank 2  
CLK5  
CLK6  
OE  
AVSS VSS  
VDD  
AVDD  
VDDL VSSL PWRDWN  
Cypress Semiconductor Corporation  
Document #: 38-07006 Rev. *I  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised February 9, 2011  
[+] Feedback  

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