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CY14MB064J_13 PDF预览

CY14MB064J_13

更新时间: 2024-02-05 20:00:25
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
30页 1886K
描述
64-Kbit (8 K x 8) Serial (I2C) nvSRAM

CY14MB064J_13 数据手册

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CY14MB064J  
CY14ME064J  
64-Kbit (8 K × 8) Serial (I2C) nvSRAM  
64-Kbit (8  
K × 8) Serial (I2C) nvSRAM  
Industry standard configurations  
Operating voltages:  
Features  
64-Kbit nonvolatile static random access memory (nvSRAM)  
Internally organized as 8 K × 8  
STORE to QuantumTrap nonvolatile elements initiated  
automatically on power-down (AutoStore) or by using I2C  
command (SoftwareSTORE) orHSBpin(HardwareSTORE)  
RECALL to SRAM initiated on power-up (Power-Up  
RECALL) or by I2C command (Software RECALL)  
Automatic STORE on power-down with a small capacitor  
(except for CY14MX064J1)  
• CY14MB064J: VCC = 2.7 V to 3.6 V  
• CY14ME064J: VCC = 4.5 V to 5.5 V  
Industrial temperature  
8- and 16-pin small outline integrated circuit (SOIC) package  
Restriction of hazardous substances (RoHS) compliant  
Overview  
The Cypress CY14MB064J/CY14ME064J combines a 64-Kbit  
nvSRAM[2] with a nonvolatile element in each memory cell. The  
memory is organized as 8 K words of 8 bits each. The embedded  
nonvolatile elements incorporate the QuantumTrap technology,  
creating the world’s most reliable nonvolatile memory. The  
SRAM provides infinite read and write cycles, while the  
QuantumTrap cells provide highly reliable nonvolatile storage of  
data. Data transfers from SRAM to the nonvolatile elements  
(STORE operation) takes place automatically at power-down  
(except for CY14MX064J1). On power-up, data is restored to the  
SRAM from the nonvolatile memory (RECALL operation). The  
STORE and RECALL operations can also be initiated by the user  
through I2C commands.  
High reliability  
Infinite read, write, and RECALL cycles  
1 million STORE cycles to QuantumTrap  
Data retention: 20 years at 85 C  
High speed I2C interface [1]  
Industry standard 100 kHz and 400 kHz speed  
Fast-mode Plus: 1 MHz speed  
High speed: 3.4 MHz  
Zero cycle delay reads and writes  
Write protection  
Hardware protection using Write Protect (WP) pin  
Software block protection for 1/4, 1/2, or entire array  
I2C access to special functions  
Nonvolatile STORE/RECALL  
8 byte serial number  
Manufacturer ID and Product ID  
Sleep mode  
Configuration  
Feature  
AutoStore  
CY14MX064J1 CY14MX064J2 CY14MX064J3  
No  
Yes  
Yes  
Yes  
Yes  
Software  
STORE  
Yes  
Low power consumption  
Hardware  
STORE  
No  
No  
Yes  
Average active current of 1 mA at 3.4 MHz operation  
Average standby mode current of 150 µA  
Sleep mode current of 8 µA  
Slave Address  
pins  
A2, A1, A0  
A2, A1  
A2, A1, A0  
Logic Block Diagram  
Serial Number  
VCC VCAP  
Manufacturer ID /  
Product ID  
Power Control  
Memory Control Register  
Command Register  
Block  
Quantum Trap  
8 K x 8  
Sleep  
STORE  
Control Registers Slave  
Memory Slave  
SRAM  
8 K x 8  
SDA  
SCL  
A2, A1, A0  
WP  
I2C Control Logic  
Slave Address  
Decoder  
Memory  
Address and Data  
Control  
RECALL  
Notes  
2
1. The I C nvSRAM is a single solution which is usable for all four speed modes of operation. As a result, some I/O parameters are slightly different than those on  
chips which support only one mode of operation. Refer to AN87209 for more details.  
2
2. Serial (I C) nvSRAM is referred to as nvSRAM throughout the datasheet.  
Cypress Semiconductor Corporation  
Document Number: 001-65051 Rev. *H  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised April 29, 2013  

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