Datasheet > CY14B101LA_1107

CY14B101LA_1107

更新时间： 2024-11-05 09:40:59

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
28页	1019K
描述
1 Mbit (128K x 8/64K x 16) nvSRAM

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中文翻译

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数据手册

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CY14B101LA_1107 数据手册

CY14B101LA

CY14B101NA

1-Mbit (128 K × 8/64 K × 16) nvSRAM

1-Mbit (128

K × 8/64 K × 16) nvSRAM

■ Packages

Features

❐ 32-pin small-outline integrated circuit (SOIC)

❐ 44-/54-pin thin small outline package (TSOP) Type II

■ 20 ns, 25 ns, and 45 ns access times

❐ 48-pin shrink small-outline package (SSOP)

❐ 48-ball fine-pitch ball grid array (FBGA)

■ Internally organized as 128 K × 8 (CY14B101LA) or 64 K × 16

(CY14B101NA)

■ Pb-free and restriction of hazardous substances (RoHS)

compliant

■ Hands off automatic STORE on power-down with only a small

capacitor

■ STORE to QuantumTrap nonvolatile elements initiated by

software, device pin, or AutoStore on power-down

Functional Description

The Cypress CY14B101LA/CY14B101NA is a fast static RAM

(SRAM), with a nonvolatile element in each memory cell. The

memory is organized as 128 K bytes of 8 bits each or 64 K words

of 16 bits each. The embedded nonvolatile elements incorporate

QuantumTrap technology, producing the world’s most reliable

nonvolatile memory. The SRAM provides infinite read and write

cycles, while independent nonvolatile data resides in the highly

reliable QuantumTrap cell. Data transfers from the SRAM to the

nonvolatile elements (the STORE operation) takes place

automatically at power-down. On power-up, data is restored to

the SRAM (the RECALL operation) from the nonvolatile memory.

Both the STORE and RECALL operations are also available

under software control.

■ RECALL to SRAM initiated by software or power-up

■ Infinite read, write, and RECALL cycles

■ 1 million STORE cycles to QuantumTrap

■ 20 year data retention

■ Single 3 V +20% to –10% operation

■ Industrial temperature

Logic Block Diagram ^{[1, 2, 3]}

V_CAP

V_CC

Quatrum Trap

1024 X 1024

A₅

A₆

A₇

A₈

A₉

POWER

CONTROL

STORE

RECALL

STORE/RECALL

CONTROL

HSB

STATIC RAM

ARRAY

1024 X 1024

A₁₂

A₁₃

A₁₄

SOFTWARE

DETECT

A₁₅

A₁₄- A₂

A₁₆

DQ₀

DQ₁

DQ₂

DQ₃

DQ₄

DQ₅

DQ₆

DQ₇

COLUMN I/O

DQ₈

DQ₉

DQ₁₀

COLUMN DEC

DQ₁₁

DQ₁₂

DQ₁₃

DQ₁₄

BLE

A₀A₁A₂A₃A₄A₁₀A₁₁

DQ₁₅

BHE

Notes

1. Address A –A for × 8 configuration and Address A –A for × 16 configuration.

2. Data DQ –DQ for × 8 configuration and Data DQ –DQ for × 16 configuration.

3. BHE and BLE are applicable for × 16 configuration only.

Cypress Semiconductor Corporation

Document #: 001-42879 Rev. *L

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised July 14, 2011

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与CY14B101LA_1107相关器件

型号	品牌	获取价格	描述	数据表
CY14B101LA_12	CYPRESS	获取价格	1-Mbit (128 K Ã 8/64 K Ã 16) nvSRAM
CY14B101LA-BA20XC	CYPRESS	获取价格	Non-Volatile SRAM, 128KX8, 20ns, CMOS, PBGA48, 6 X 10 MM, 1.20 MM HEIGHT, ROHS COMPLIANT,
CY14B101LA-BA20XCT	CYPRESS	获取价格	Non-Volatile SRAM, 128KX8, 20ns, CMOS, PBGA48, 6 X 10 MM, 1.20 MM HEIGHT, ROHS COMPLIANT,
CY14B101LA-BA20XIT	CYPRESS	获取价格	Non-Volatile SRAM, 128KX8, 20ns, CMOS, PBGA48, 6 X 10 MM, 1.20 MM HEIGHT, ROHS COMPLIANT,
CY14B101LA-BA25XCT	CYPRESS	获取价格	Non-Volatile SRAM, 128KX8, 25ns, CMOS, PBGA48, 6 X 10 MM, 1.20 MM HEIGHT, ROHS COMPLIANT,
CY14B101LA-BA25XI	CYPRESS	获取价格	Non-Volatile SRAM, 128KX8, 25ns, CMOS, PBGA48, FBGA-48
CY14B101LA-BA25XI	INFINEON	获取价格	nvSRAM (non-volatile SRAM)
CY14B101LA-BA25XIT	INFINEON	获取价格	nvSRAM (non-volatile SRAM)
CY14B101LA-BA45XI	CYPRESS	获取价格	1 Mbit (128K x 8/64K x 16) nvSRAM
CY14B101LA-BA45XI	INFINEON	获取价格	nvSRAM (non-volatile SRAM)

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