CXD2510Q
CD Digital Signal Processor
Description
80 pin QFP (Plastic)
The CXD2510Q is a digital signal processor LSI for
CD players and is equipped with the following functions.
• Wide frame jitter margin (±28 frames) due to a built-
in 32K RAM
-L051
-L01
• Bit clock, which strobes the EFM signal, is
generated by the digital PLL
• EFM data demodulation
• Enhanced EFM frame sync signal protection
• Refined super strategy-based powerful error correction
C1: double correction, C2: quadruple correction
• Quadruple-speed, double-speed and variable pitch
playback
• Noise reduction during track jumps
• Auto zero-cross mute
• Subcode demodulation and Sub Q data error
correction
• Digital spindle servo (built-in oversampling filter)
• 16-bit traverse counter
• Asymmetry compensation circuit
• Serial bus-based CPU interface
• Error correction monitor signals are output from a
new CPU interface.
Recommended Operating Conditions
• Supply voltage
• Operating temperature Topr
VDD
4.50 to 5.50
–20 to +75
V
°C
The VDD (min.) for the CXD2510Q varies according
to the playback speed and built-in VCO selection.
The VDD (min.) is 4.50 V when high speed VCO
and quadruple-speed playback are selected
(variable pitch off). The VDD (min.) for the
CXD2510Q under various conditions are as shown
in the following table.
VDD (min.) [V]
Playback
speed
• Servo auto sequencer
VCO high-speed VCO normal-speed
• Fine search which performs high-precision track
jumps
• Digital audio interface output
• Digital level meter, peak meter
• Bilingual compatible
× 4
× 2
× 2
× 1
× 1
4.50
4.00
3.40
3.40
3.40
—
1
2
—
4.00
3.40
3.40
Features
• All digital signals processed with a single chip
Dashes indicate that there is no assurance of the
processor operating. All values are for variable pitch off.
during playback
• High-integrated mounting possible due to a built-in
RAM
1
When the internal operation of the LSI is set to
normal-speed playback and the operating clock
of the signal processor is doubled, double-speed
playback results.
Structure
Silicon gate CMOS IC
2
When the internal operation of the LSI is set to
double-speed mode and the crystal oscillating
frequency is halved in low power consumption
mode, normal-speed playback results.
Absolute Maximum Ratings
• Supply voltage
• Input voltage
VDD
VI
–0.3 to +7.0
–0.3 to +7.0
V
V
(VSS – 0.3V to VDD + 0.3V)
–0.3 to +7.0
–40 to +125 °C
Input/output Capacitances
• Output voltage
• Storage temperature Tstg
• Supply voltage difference
VO
V
• Input capacitance
• Output capacitance
CI
CO
12 (max.)
12 (max.)
pF
pF
for high impedance
VDD = VI = 0V
fM = 1MHz
Vss – AVss –0.3 to +0.3
VDD – AVDD –0.3 to +0.3
V
V
Note) Measurement conditions
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E94412A11