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CXD2529Q PDF预览

CXD2529Q

更新时间: 2024-09-19 22:35:35
品牌 Logo 应用领域
索尼 - SONY 消费电路商用集成电路数字信号处理器
页数 文件大小 规格书
64页 670K
描述
CD Digital Signal Processor

CXD2529Q 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:QFP, QFP100,.7X.9
针数:100Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.88
Is Samacsys:N商用集成电路类型:CONSUMER CIRCUIT
JESD-30 代码:R-PQFP-G100JESD-609代码:e0
长度:20 mm功能数量:1
端子数量:100最高工作温度:75 °C
最低工作温度:-20 °C封装主体材料:PLASTIC/EPOXY
封装代码:QFP封装等效代码:QFP100,.7X.9
封装形状:RECTANGULAR封装形式:FLATPACK
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.5/5,5 V
认证状态:Not Qualified座面最大高度:3.1 mm
子类别:Other Consumer ICs最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):3.4 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL EXTENDED
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.65 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:14 mm
Base Number Matches:1

CXD2529Q 数据手册

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CXD2529Q  
CD Digital Signal Processor  
For the availability of this product, please contact the sales office.  
Description  
100 pin QFP (Plastic)  
The CXD2529Q is a digital signal processor LSI for  
CD players and is equipped with built-in digital filters,  
zero detection circuit, 1-bit DAC, and analog low-  
pass filter on a single chip.  
Features  
Digital Signal Processor (DSP) Block  
Playback mode supporting CAV (Constant Angular  
Velocity)  
Frame jitter-free  
Allows 0.5 to double-speed continuous playback  
Allows relative rotational velocity readout  
Supports external spindle control  
Wide capture range mode  
Absolute Maximum Ratings  
Supply voltage  
Input voltage  
VDD  
VI  
–0.3 to +7.0  
–0.3 to +7.0  
V
V
(Vss – 0.3V to VDD + 0.3V)  
Spindle rotational velocity following method  
– Supports normal-speed and double-speed playback  
16K RAM  
Output voltage  
VO  
–0.3 to +7.0  
–40 to +125  
V
°C  
Storage temperature Tstg  
Supply voltage difference  
VSS – AVSS  
EFM data demodulation  
–0.3 to +0.3  
–0.3 to +0.3  
V
V
Enhanced EFM frame sync signal protection  
SEC strategy-based error correction  
Subcode demodulation and Sub Q data error detection  
Digital spindle servo  
VDD – AVDD  
Note) AVDD includes XVDD, and AVSS includes XVSS.  
Recommended Operating Conditions  
Supply voltage  
Operating temperature Topr  
Note) The VDD (min.) for the CXD2519Q varies  
16-bit traverse counter  
VDD  
3.4 to 5.25  
–20 to +75  
V
°C  
Asymmetry compensation circuit  
Serial bus-based CPU interface  
Error correction monitor signals, etc. are output  
from a new CPU interface.  
according to the playback speed selection.  
VDD (min.) [V]  
Playback  
Servo auto sequencer  
Digital audio interface output  
Digital peak meter  
speed  
CD-DSP block  
3.4V  
DAC block  
4.5V  
× 2  
× 1  
× 1  
Digital Filter, DAC, Analog Low-Pass Filter Block  
DBB (Digital Bass Boost)  
Supports double-speed playback  
Digital de-emphasis  
Digital attenuation function  
Zero detection function  
3.4V  
3.4V  
1
3.4V  
1
When the internal operation of the CD-DSP  
side is set to double-speed mode and the  
crystal oscillation frequency is halved,  
normal-speed playback results.  
8fs oversampling digital filter  
S/N ratio: 100dB or more (master clock: 384fs typ.)  
Logical value: 109dB  
Input/Output Capacitances  
Input pin  
Output pin  
CI  
CO  
12 (max.)  
12 (max.)  
pF  
pF  
THD + N: 0.007% or less (master clock: 384fs typ.)  
Rejection band attenuation: –60dB or more  
Note) Measurement conditions  
VDD = VI = 0V  
fM = 1MHz  
Applications  
CD players  
Structure  
Silicon gate CMOS IC  
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by  
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the  
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.  
– 1 –  
E96651A73  

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