Datasheet > CX6211(144TFBGA)

CX6211(144TFBGA)

更新时间： 2024-09-17 06:59:55

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艾迪悌 - IDT		/
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2页	65K
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Programmable Logic Device

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CX6211(144TFBGA) 数据手册

Product Brief

CX6200

Structured ASIC with USB 2.0 PHY

Product Description

The CX6200 product family—a member of the latest generation of Structured ASICs from ChipX—

combines built-in, silicon-proven, industry standard PHYs for USB 2.0 High Speed On-the-Go (OTG)

with the well-proven X-Cell™ Structured ASIC architecture to provide industry leading performance

using the UMC eight-metal high-speed 0.13-mm deep submicron process. Up to four metal layers are

used for customization, allowing ChipX to hold wafers at bank with most of the processing

completed. Prototypes are manufactured, assembled, tested, and shipped in just 4 to 5 weeks.

The built-in, silicon-proven USB 2.0 HS OTG PHY, in combination with ChipX validated,

synthesizable processors and USB Host, Device, and OTG controllers, form a complete,

interoperability-proven, USB subsystem capable of achieving USB-IF compliance. You can also use

your own USB controller and processor of choice where desired. The USB subsystem on the

CX6200 family of products removes complexity and risk of IP selection and IP interoperability testing,

enabling faster time to market.

Table 1. CX6200 Product Matrix

Part Number Usable Gates Memory (Kbits)

Maximum

PLL

USB 2.0

[KGates]

(9-Kb Banks) Configurable 10 MHz–1 GHz OTG PHY

I/O*

Packages

CX6210

CX6211

CX6212

CX6214

CX6215

CX6216

CX6220

CX6222

CX6237

CX6273

CX6275

CX6277

140

324 (36)

306 (34)

288 (32)

306 (34)

270 (30)

234 (26)

288 (32)

252 (28)

216 (24)

1044 [116]

918 [102]

846 [94]

120

130

140

144

150

160

170

184

200

238

254

280