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CS7054

更新时间: 2024-11-16 03:26:59
品牌 Logo 应用领域
安森美 - ONSEMI 控制器
页数 文件大小 规格书
12页 91K
描述
Low Side PWM FET Controller

CS7054 数据手册

 浏览型号CS7054的Datasheet PDF文件第2页浏览型号CS7054的Datasheet PDF文件第3页浏览型号CS7054的Datasheet PDF文件第4页浏览型号CS7054的Datasheet PDF文件第5页浏览型号CS7054的Datasheet PDF文件第6页浏览型号CS7054的Datasheet PDF文件第7页 
CS7054  
Low Side PWM FET  
Controller  
The CS7054 is a monolithic integrated circuit designed primarily to  
control the rotor speed of permanent magnet, direct current (DC)  
brush motors. It drives the gate of an N channel power MOSFET or  
IGBT with a user–adjustable, fixed frequency, variable duty cycle,  
pulse width modulated (PWM) signal. The CS7054 can also be used to  
control other loads such as incandescent bulbs and solenoids.  
Inductive current from the motor or solenoid is recirculated through an  
external diode.  
http://onsemi.com  
DIP–14  
N SUFFIX  
CASE 646  
14  
The CS7054 accepts a DC level input signal of 0 to 5.0 V to control  
the pulse width of the output signal. This signal can be generated by a  
potentiometer referenced to the on–chip 5.0 V linear regulator, or a  
filtered 0% to 100% PWM signal also referenced to the 5.0 V  
regulator.  
The IC is placed in a sleep state by pulling the CTL lead below 0.5 V.  
In this mode everything on the chip is shut down except for the  
on–chip regulator and the overall current draw is less than 275 µA.  
There are a number of on–chip diagnostics that look for potential  
failure modes and can disable the external power MOSFET.  
1
SO–16L  
DW SUFFIX  
CASE 751G  
16  
1
PIN CONNECTIONS AND  
MARKING DIAGRAMS  
1
14  
OUTPUT  
GND  
V
CC  
PGND  
INH  
Features  
FLT  
200 mA Peak PWM Gate Drive Output  
C
R
I
OSC  
ADJ  
Patented Voltage Compensation Circuit  
100% Duty Cycle Capability  
5.0 V, ± 3.0% Linear Regulator  
Low Current Sleep Mode  
I
I
OSC  
SENSE+  
CTL  
NC  
SENSE–  
V
REG  
DIP–14  
Overvoltage Protection  
Overcurrent Protection of External MOSFET/IGBT  
Output Inhibit  
1
16  
OUTPUT  
V
CC  
GND  
FLT  
NC  
PGND  
INH  
C
OSC  
R
CTL  
I
I
I
OSC  
ADJ  
SENSE+  
NC  
SENSE–  
NC  
V
REG  
SO–16L  
A
WL, L  
YY, Y  
= Assembly Location  
= Wafer Lot  
= Year  
WW, W = Work Week  
ORDERING INFORMATION  
Device  
Package  
Shipping  
CS7054YN14  
25 Units/Rail  
46 Units/Rail  
DIP–14  
SO–16L  
SO–16L  
CS7054YDW16  
CS7054YDWR16  
1000 Tape & Reel  
Semiconductor Components Industries, LLC, 2001  
1
Publication Order Number:  
January, 2001 – Rev. 12  
CS7054/D  

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