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CS19202CBI30 PDF预览

CS19202CBI30

更新时间： 2024-11-18 04:12:35
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AMCC 异步传输模式ATM
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2页 42K
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STS-192 SONET/SDH FRAMER AND POS/ATM MAPPER

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CS19202CBI30 数据手册

 浏览型号CS19202CBI30的Datasheet PDF文件第2页 
Part Number - S19202CBI30  
Product Brief Revision 3.1 - January 2002  
PRODUCT BRIEF  
GANGES  
STS-192 SONET/SDH FRAMER AND POS/ATM MAPPER  
General Description  
Features  
• Supports full duplex mapping of ATM cells or packets for a  
single STS-192c/AU-4-64c, four STS-48c/AU-4-16c or six-  
teen STS-12c/AU-4-4c SONET/SDH payloads.  
The Ganges IC is a highly integrated VLSI device that pro-  
vides full duplex mapping of Packets or ATM cells into  
SONET/SDH payloads at rates up to 9.95Gb/s.  
• Supports a single STS-192/STM-64 or quad STS-48/STM-  
16 line interfaces on the line side and on the protection  
port. Each STS-48/STM-16 can support a concatenated  
payload or can be channelized down to STS-12c/AU-4-4c.  
Ganges provides full section and line overhead processing  
for either a single STS-192/STM-64, or four STS-48/STM-16.  
It supports framing, scrambling and descrambling, alarm sig-  
nal insertion and detection, and bit interleaved parity (B1/B2)  
processing. It also provides path overhead processing for  
STS-192c/AU-4-64c, STS-48c/AU-4-16c or STS-12c/AU-4-  
4c SONET/SDH payloads and includes bit interleaved parity  
(B3) processing.  
• Terminates and generates SONET/SDH section, line, &  
path layers on the line side and APS port, with transport/  
section E1, E2, F1 and DCC overhead interfaces in both  
transmit and receive directions.  
The automatic protection switching (APS) port of the Ganges  
supports generation and termination of SONET/SDH section  
and line, as well as TOH insertion and extraction. This allows  
inter-device protection switching between two Ganges  
devices or intra-device protection between two fiber optics  
modules.  
• Supports independent loop timing when in quad STS-48/  
STM-16 mode.  
• Supports protection switching (APS) between two Ganges  
devices or between two fiber optics modules  
• Provides an Optical Internetworking Forum (OIF) SFI-4  
compliant 622.08 MHz, 16-bit bus LVDS interface on the  
line side in both the TX and RX directions.  
The Ganges is SONET/SDH standards compliant with  
Bellcore GR-253, ITU G.707, and ANSI T1.105 -1995.  
• Provides a 64-bit, 200 MHz FlexBus 4 system interface  
that supports the transfer of either packets or ATM cells.  
Applications  
• Support mixed ATM and POS data termination, config-  
urable on a per-tributary basis  
• Core ATM switches and IP Routers (POS)  
• ATM, POS and Frame Relay line cards in Edge and Metro  
Switches  
• 16-bit synchronous microprocessor interface for configura-  
tion, control, and status monitoring.  
• Direct Mapping of any traffic type in SONET/SDH STS-192/  
STM-64 and STS-48/STM-16 payloads  
• Packaged in a 624-pin CBGA.  
• Implemented in .18 micron, 1.8V and 2.5V technology.  
S19202 Block Diagram  
PROT TX  
TOH INSERT  
SYSTEM  
FR GEN x4  
MICROPROCESSOR I/F  
INTRFC/  
Control  
ATM/POS  
MUX  
SPE/VC  
GENERATOR  
POH  
GENERATION  
x16  
/
TX_CLK_OUT[1:4]  
HDLC /ATM  
Proc  
STX_DATA_IN[63:0]  
FIFO  
x16  
TX_DATA_OUT[15:0]  
FRGEN  
x4  
SEL  
x16  
x16  
FRMR  
LBK  
SEL  
MONITOR  
RX_DATA_IN[15:0]  
RX_CLK_IN_[1:4]  
S
E
L
SYSTEM  
INTRFC/  
POH  
x4  
SRX_DATA_OUT[63:0]  
Control  
POINTER  
INTERPRETER  
HDLC /ATM  
x16  
Proc  
ATM/POS  
FIFO  
x16  
x16  
RX PROT  
FRM x4  
JTAG  
LOC  
DET  
TOH EXTRACT  
x16  
Production Release Information  
- The information con-  
tained in this document is about a product in its fully tested  
and characterized stage. All features described herein are  
supported. Contact AMCC for updates to this document and  
the latest product status.  
AMCC  
12

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