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CS19208CBI PDF预览

CS19208CBI

更新时间: 2024-11-18 04:12:35
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AMCC /
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4页 131K
描述
OC-192/48/12/3 DW/FEC/PM and ASYNC Mapper Device

CS19208CBI 数据手册

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Product Brief  
Part Number S19208CBI, Revision 1.4, Jan 2003  
Niagara  
OC-192/48/12/3 DW/FEC/PM and ASYNC Mapper Device  
Features  
Enhanced Gain Forward Error Correction with G.709 ODU  
• 10.71, 10.66, and 11.1 Gbps enhanced FEC with >8dB coding gain  
G.709 ODU - 2 Synchronous and Asynchronous mapping  
• 1 x OC – 192/STM-64 mapping (239,237)  
G.709 overhead processing and nominal rate expansion  
• Comprehensive channel statistics gathering  
• Corrected bits, bytes  
• Direct map (239,238) into ODU – 2  
G.709 ODU - 1 Synchronous and Asynchronous mapping  
• 1 x OC – 48/STM-16 mapping (239,237)  
• Corrected zeros, ones (with outputs)  
• Uncorrectable sub-frame count  
• Direct map (239,238) into ODU – 1  
Broad Interface Compatibility  
• 16 bit, 622 Mbps LVDS interface (OIF MSA compliant) 10 Gbps  
interface  
G.709 Overhead processing  
• Bi-directional add-drop ODU – 1, ODU – 2  
• Bi-direction G.709 Overhead Processing  
• Dedicated GCC ports  
• Compatible with AMCC Hudson, Ganges, S3091/92, S3097/98,  
S19211, S3193/S3094, and S3474  
Client and Line side loop-back  
• Client-side loopback on single 10 Gbps interface  
Ingress and Egress SONET/SDH Performance Monitoring/  
Injection  
• 1 x OC-192/48/12/3 TOH add-drop and processing  
• Line loopback on 10 Gbps interface  
• 8B/10B Monitoring  
Support For System Test and Diagnostics  
• Can synthesize SONET frame  
• 10GE Monitoring  
• SONET/SDH section and line termination  
• TOH add-drop port  
• Error injection capability for verification of remote error reporting  
Test set compliant pseudo-random sequence generation/analysis  
• LOS, OOF, LOF detection  
General Purpose Processor Interface  
• Glueless interface to MPC860, 25 MHz to 52 MHz  
• B1, B2 monitoring with programmable Signal Degrade and Signal  
Fail thresholds  
• J0 Monitoring, SDH and SONET modes  
• Support for Protection Switching  
• Dual Mode Interface also supports Intel processors  
• Interrupt Driven or Polled mode operation  
• K1, K2 monitoring for APS changes, line AIS and line RDI  
• Automatic, interrupt-driven, or manual AIS insertion  
• Frame boundary output  
Additional Protocol Support  
• FEC Frame Synchronous scrambling  
• Programmable sequence detection  
Industry Standard RS(255,239) Forward Error Correction with 6.2  
dB Coding Gain (at 10 CER)  
G.709 Compliant Frame Structure  
Low Power .18 u CMOS Technology  
• 1.8 Volt core operation  
-15  
• 2.5 Volt I/O  
• Compatible with AMCC S19203 (Hudson)  
Figure 1: Block Diagram  
IngressEgress  
SONET/SDH  
TOH Add/Drop  
OTN Network/Line  
Interface  
Client or OTN  
Interface  
Ingress/EgressOD  
U-2 OH Add/Drop  
Pattern  
& Err  
Analysis  
R-S  
FEC  
Encoder  
OC-192  
PM  
10GE  
PM  
EFEC  
Decoder  
PN gen  
Err Ins  
BYPASS  
BYPASS  
BYPASS  
BYPASS  
BYPASS  
BYPASS  
R-S  
FEC  
Decoder  
Pattern  
& Err  
Analysis  
PN gen  
Err Ins  
EFEC  
Encoder  
OC-192  
PM  
10GE  
PM  
Register  
Map  
Interrupt  
Control  
SFI-4 (10 GBPS)  
SFI-4 (10 GBPS)  
8 or 16 uP I/F  
Final/Production ReleaseInformation - The information contained in this docu-  
ment is about a product in its fully tested and characterized phase. All features  
described herein are supported. Contact AMCC for updates to this document and  
the latest product status.  
Empowering Intelligent Optical Networks  

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