Product Brief
HUDSON 2.0
Part Number S19203CBI20, Revision 1.3, May 2003
Variable Rate Digital Wrapper Framer/Deframer, PM, and FEC Device
The Hudson is a fully integrated, Variable Rate Digital Wrapper Framer/Deframer, Performance Monitor, and Forward Error Correction (FEC)
device supporting the Digital Wrapper transmission standards for OTU1, OTU2, ODU1, ODU2, OPU1, and OPU2 as specified in G.709. The
Hudson implements Performance Monitoring and overhead processing functions on the Digital Wrapper overhead bytes. In addition, the
device contains SONET/SDH Performance Monitoring to verify the validity of the SONET/SDH OC-192 client data. The device can operate
from a low rate of 6.25 MHz to a high rate of 693.483 MHz. Data entering and leaving the chip can be optionally deframed and framed,
descrambled and scrambled, and decoded and encoded with forward error correction information.
• Core logic runs on a 1.8 V power supply to reduce power con-
sumption and LVCMOS I/O are 3.3 V compatible.
• Support for System test and diagnostics: internal BER generator,
PRBS pattern generator and pattern analyzer for bit error rate
testing capability.
• Two independent 16-bit parallel LVDS input and output ports at
up to 693.483 MHz (11.096 Gbps).
• Four programmable integer clock dividers to simplify clock gener-
ation.
• Datapath options: Configurable as two completely independent
data stream for full duplex operation. Configurable as a single
data stream for regenerator operation with dual redundant I/O for
optional protection switching. Either input port can be directly
connected to either output port for loopback testing or bypass
operation.
• Support for signal aggregation to higher rates via chip synchroni-
zation feature.
• General Purpose Processor Interface: Gluess interface to
MPC860, 25 MHz to 50 MHz bus speed. Also compatible with
Intel microprocessor bus via Busmode selector.
• Supports SONET OC-192 Performance Monitoring at the input of
the encoder side and at the output of the decoder side.
• Low power: 0.18 micron CMOS technology.
Applications
• Supports G.709 “Interfaces for the optical transport network
(OTN)” standard including specified frame structure, all overhead
monitoring and processing, Maintenance signals, synchronous
and asynchronous mapping and demapping.
• 10 Gigabit Digital Wrapper Performance Monitor and Framer
• Protocol Independent DWDM Metropolitan Area Networks
• Optical Cross-connects
• ON/OFF control of Reed-Solomon (255,239) FEC Encoding/
Decoding and error correction.
• OC-192 Port interface
• Fiber optic terminators, repeaters, and test equipment
Figure 1: Block Diagram
Hudson 2.0
DU P_OUT _SEL[1:0]
D EC _IN_SEL[1:0]
Decode (DEC) Side
Pattern
Analyzer
INPUT_PORT _SW AP
0
O UTPUT_PO RT_SW AP
DECO DEIN[15:0]
DEC
1:8
Demux
00
10
01, 11
01
11
00
DEC OH
Framer
1
0
1
00,10
01
Rate
Match
FIFO
DEC OH
DEC
SONET
PM
00
10
DECRXCLK
FEC
Decoder
Ins
&
DUPO
UT 1:8
Mux
DUPLEXO UT[15:0]
DUPTXCLK_OUT
Scrambler
Clock
Divider
DECRXCLK_DIV
Clock
Divider
DUPTXCLK_DIV
RX_OH_CLK
RX_OH_DATA[7:0]
DRO PFP
DEC O H
DROPSFP
Mon/Drop
Sync
Buffer
DEC_INSCLK
DEC_INS_FP
DEC_INS_SFP
DECINS[7:0]
DEC_INS_EN
ENC_DRPCLK
ENC_DRP[7:0]
ENC_DRP_FP
ENC_DRP_SFP
1
0
O CH
Descram
SC/O H
Mon/Drop
00, 01
ENC
SONET
PM
DUPIN
1:8
Demux
1
DUP O H
Framer
DUPLEXIN[15:0]
1
0
00
10
ENC
8:1
Mux
&
ENC O H
Frame
DUPRXCLK
ENCDATAOUT[15:0]
ENCTXCLK
0
Rate
Match
FIFO
0
1
10
G en
&
IN PUT_PO RT_SW AP
01
FEC
Encoder
O UTPU T_POR T_SW AP
Pattern
Generator
EN C_IN_SEL
Clock
Divider
TX_OH_CLK
DUPRXCLK_DIV
INSFP
ENC O H
Add
PAT _GEN_ON
TX_OH_DATA[7:0]
INSSFP
TX_OH_INS
Clock
Divider
ENC_O UT_SEL[1:0]
ENCTXCLK_DIV
Encode (ENC) Side
FINAL/PRODUCTION RELEASE Information - The information contained in this
document is about a product in its fully tested and characterized phase. All fea-
tures described herein are supported. Contact AMCC for updates to this docu-
ment and the latest product status.
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