Datasheet > CDP68HC68P1M96

CDP68HC68P1M96

更新时间： 2024-11-29 14:48:27

品牌	Logo	应用领域
瑞萨 - RENESAS		光电二极管外围集成电路
页数	文件大小	规格书
10页	78K
描述
SPECIALTY MICROPROCESSOR CIRCUIT, PDSO16, PLASTIC, MS-012AC, SOIC-16

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CDP68HC68P1M96 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	SOIC	包装说明：	PLASTIC, MS-012AC, SOIC-16
针数：	16	Reach Compliance Code：	not_compliant
HTS代码：	8542.31.00.01	风险等级：	5.69
Is Samacsys：	N	JESD-30 代码：	R-PDSO-G16
JESD-609代码：	e0	长度：	9.9 mm
湿度敏感等级：	1	位数：	8
端子数量：	16	最高工作温度：	85 °C
最低工作温度：	-55 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装等效代码：	SOP16,.25
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	240	电源：	5 V
认证状态：	Not Qualified	座面最大高度：	1.75 mm
子类别：	Parallel IO Port	最大供电电压：	6 V
最小供电电压：	3 V	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	OTHER	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	3.9 mm	uPs/uCs/外围集成电路类型：	MICROPROCESSOR CIRCUIT
Base Number Matches：	1

CDP68HC68P1M96 数据手册

CDP68HC68P1

CMOS Serial 8-Bit Input/Output Port

October 2000

Features

Description

• Fully Static Operation

The CDP68HC68P1 is a serially addressed 8-bit Input/Out-

put port that allows byte or individual bit control. It consists of

three registers, an output buffer and control logic. Data is

shifted in and out of the device via shift register that utilizes

the SPI (Serial Peripheral Interface) bus. The I/O port data

ﬂow is controlled by the Data Direction Register and data is

stored in the Data Register that outputs or senses the logic

levels at the buffered I/O pins. All inputs, including the serial

interface are Schmitt triggered. This device also features a

compare function that compares the data register and port

pin values for 4 programmable conditions and sets a

software accessible ﬂag if the condition is satisﬁed. The user

also has the option of bit-set or bit-clear when writing to the

data register.

• Operating Voltage Range 3-6V

• Compatible with Intersil/Motorola SPI Bus

• 2 External Address Pins Tied to V

Up to 4 Devices to Share the Same Chip Enable

or V to Allow

• Versatile Bit-Set and Bit-Clear Capability

• Accepts Either SCK Clock Polarity - SCK Voltage

Level is Latched When Chip Enable Goes Active

• All Inputs are Schmitt-Trigger

• 8-Bit I/O Port - Each Bit can be Individually

Programmed as an Input or Output Via an 8-Bit Data

Direction Register

Ordering Information

• Programmable On Board Comparator

TEMP.

RANGE ( C)

PKG.

NO.

PART NUMBER

CDP68HC68P1E

CDP68HC68P1M

CDP68HC68P1D

PACKAGE

16 Ld PDIP

16 Ld SOIC

16 Ld SBDIP

• Simultaneous Transfer of Compare Information to

CPU During Read or Write - Separate Access Not

Required

-55 to 85

E16.3

-55 to 85

M16.15

D16.3

-55 to 125

Pinout

CDP68HC68P1

(PDIP, SOIC, SBDIP)

(D, E, M, SUFFIX)

TOP VIEW

16 V

15 D1

MISO

MOSI

SCK

14 D2

13 D3

12 D4

11 D5

10 D6

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

File Number 1858.2

12 3 4 5 6 7...10

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与CDP68HC68P1M96相关器件

型号	品牌	获取价格	描述	数据表
CDP68HC68P2	ETC	获取价格
CDP68HC68P2Z	ETC	获取价格	Octal Peripheral Driver
CDP68HC68R1	ETC	获取价格
CDP68HC68R1E	ROCHESTER	获取价格	Standard SRAM, 128X8, CMOS, PDIP8,
CDP68HC68R2	ETC	获取价格
CDP68HC68R2E	RENESAS	获取价格	256X8 STANDARD SRAM, PDIP8
CDP68HC68R2EX	RENESAS	获取价格	CDP68HC68R2EX
CDP68HC68S1	INTERSIL	获取价格	Serial Multiplexed Bus Interface
CDP68HC68S1E	INTERSIL	获取价格	Serial Multiplexed Bus Interface
CDP68HC68S1M	INTERSIL	获取价格	Serial Multiplexed Bus Interface

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