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CDP68HC68T1_07 PDF预览

CDP68HC68T1_07

更新时间： 2024-11-30 04:11:51
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英特矽尔 - INTERSIL 时钟
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23页 400K
描述
CMOS Serial Real-Time Clock With RAM and Power Sense/Control

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CDP68HC68T1_07 数据手册

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CDP68HC68T1  
®
Data Sheet  
October 29, 2007  
FN1547.8  
CMOS Serial Real-Time Clock With RAM  
and Power Sense/Control  
Features  
• SPI (Serial Peripheral Interface)  
The CDP68HC68T1 Real-Time Clock provides a  
• Full Clock Features  
time/calendar function, a 32 byte static RAM, and a 3 wire  
Serial Peripheral Interface (SPI Bus). The primary function of  
the clock is to divide down a frequency input that can be  
supplied by the on-board oscillator in conjunction with an  
external crystal or by an external clock source. The internal  
oscillator can operate with a 32kHz, 1MHz, 2MHz, or 4MHz  
crystal. An external clock source with a 32kHz, 1MHz, 2MHz,  
4MHz, 50Hz or 60Hz frequency can be used to drive the  
CDP68HC68T1. The time registers hold seconds, minutes,  
and hours, while the calendar registers hold day-of-week,  
date, month, and year information. The data is stored in BCD  
format. In addition, 12 or 24 hour operation can be selected.  
In 12 hour mode, an AM/PM indicator is provided. The T1  
has a programmable output which can provide one of seven  
outputs for use elsewhere in the system.  
- Seconds, Minutes, Hours (12/24, AM/PM), Day of  
Week, Date, Month, Year (0 to 99), Automatic Leap Year  
• 32 Wordx8-Bit RAM  
• Seconds, Minutes, Hours Alarm  
• Automatic Power Loss Detection  
• Low Minimum Standby (Timekeeping) Voltage . . . . . 2.2V  
• Selectable Crystal or 50/60Hz Line Input  
• Buffered Clock Output  
• Battery Input Pin that Powers Oscillator and also  
Connects to V  
Pin When Power Fails  
DD  
• Three Independent Interrupt Modes  
- Alarm  
- Periodic  
Computer handshaking is controlled with a “wired-OR” interrupt  
output. The interrupt can be programmed to provide a signal as  
the result of:  
- Power-Down Sense  
• Pb-Free Available (RoHS Compliant)  
1. An alarm programmed to occur at a predetermined  
combination of seconds, minutes, and hours.  
2. One of 15 periodic interrupts ranging from sub-second to  
once per day frequency.  
3. A power fail detect. The PSE output and the V  
SYS  
input are  
used for external power control. The CPUR output is  
available to reset the processor under power-down  
conditions. CPUR is enabled under software control and  
can also be activated via the CDP68HC68T1’s watchdog. If  
enabled, the watchdog requires a periodic toggle of the CE  
pin without a serial transfer.  
Pinouts  
CDP68HC68T1  
(16 LD PDIP, SOIC)  
TOP VIEW  
CDP68HC68T1  
(20 LD SOIC)  
TOP VIEW  
1
CLKOUT  
CPUR  
INT  
16  
15  
V
1
2
3
4
5
6
7
8
9
20 VDD  
CLK OUT  
CPUR  
INT  
DD  
2
3
4
5
6
7
8
XTAL OUT  
XTAL OUT  
19  
18  
17  
16  
15  
14  
14 XTAL IN  
XTAL IN  
NC  
SCK  
V
V
NC  
13  
12  
BATT  
MOSI  
MISO  
SCK  
V
SYS  
BATT  
11 LINE  
10 POR  
MOSI  
V
SYS  
CE  
NC  
MISO  
CE  
V
9
PSE  
13 NC  
12  
SS  
V
LINE  
SS  
PSE 10  
11  
POR  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.  
Copyright Harris Corporation 1997. Copyright Intersil Americas Inc. 2001, 2004-2007. All Rights Reserved  
All other trademarks mentioned are the property of their respective owners.  
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