Datasheet > CDP68HC68W1

CDP68HC68W1

更新时间： 2024-11-28 22:19:59

品牌	Logo	应用领域
英特矽尔 - INTERSIL		/
页数	文件大小	规格书
9页	46K
描述
CMOS Serial Digital Pulse Width Modulator

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数据手册

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CDP68HC68W1 数据手册

CDP68HC68W1

CMOS Serial Digital Pulse Width Modulator

March 1998

Features

Description

• Programmable Frequency and Duty Cycle Output

The CDP68HC68W1 modulates a clock input to supply a

variable frequency and duty-cycle output signal. Three 8-bit

registers (pulse width, frequency and control) are accessed

serially after power is applied to initialize device operation.

The value in the pulse width register selects the high

duration of the output period. The frequency register byte

divides the clock input frequency and determines the overall

output clock period. The input clock can be further divided by

two or a low power mode may be selected by the lower two

bits in the control register. A comparator circuit allows

threshold control by setting the output low if the input at the

• Serial Bus Input; Compatible with Motorola/Intersil

SPI Bus, Simple Shift-Register Type Interface

• 8 Lead PDIP Package

• Schmitt Trigger Clock Input

• 4V to 6V Operation, -40 C to 85 C Temperature Range

• 8MHz Clock Input Frequency

Pinout

V pin rises above 0.75V. The CDP68HC68W1 is supplied in

an 8 lead PDIP package (E sufﬁx).

CDP68HC68W1

(PDIP)

TOP VIEW

Ordering Information

CLK

TEMP. RANGE

PKG.

NO.

PWM

SCK

PART NUMBER

( C)

PACKAGE

CDP68HC68W1E

-40 to 85

8 Ld PDIP

E8.3

DATA

Block Diagram

PWM

INPUT CLK

MODULATOR

LOGIC

CLK

8 - STAGE RIPPLE

COUNTER

8 - STAGE RIPPLE

COUNTER

RESET

LOAD

PULSE - WIDTH

DATA REGISTER

FREQUENCY

DATA REGISTER

LOAD

DATA

8 - STAGE SHIFT

CONTROL REGISTER

2 - STAGE SHIFT

LOAD

COMPARATOR

SCK

5 - STAGE 24 - STATE

COMPARATOR

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

File Number 1919.3

12 3 4 5 6 7...9

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