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CD74HCT7046AM PDF预览

CD74HCT7046AM

更新时间： 2024-01-18 09:24:34
品牌 Logo 应用领域
德州仪器 - TI 光电二极管
页数 文件大小 规格书
26页 301K
描述
Phase-Locked Loop with VCO and Lock Detector

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CD74HCT7046AM 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Active零件包装代码：SOIC
包装说明：SOIC-16针数：16
Reach Compliance Code：compliantHTS代码：8542.39.00.01
Factory Lead Time：1 week风险等级：5.14
Is Samacsys：N模拟集成电路 - 其他类型：PHASE LOCKED LOOP
JESD-30 代码：R-PDSO-G16JESD-609代码：e4
长度：9.9 mm湿度敏感等级：1
功能数量：1端子数量：16
最高工作温度：125 °C最低工作温度：-55 °C
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP16,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：260
电源：5 V认证状态：Not Qualified
座面最大高度：1.58 mm子类别：PLL or Frequency Synthesis Circuits
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：MILITARY
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：3.91 mm
Base Number Matches：1

CD74HCT7046AM 数据手册

 浏览型号CD74HCT7046AM的Datasheet PDF文件第1页浏览型号CD74HCT7046AM的Datasheet PDF文件第2页浏览型号CD74HCT7046AM的Datasheet PDF文件第3页浏览型号CD74HCT7046AM的Datasheet PDF文件第5页浏览型号CD74HCT7046AM的Datasheet PDF文件第6页浏览型号CD74HCT7046AM的Datasheet PDF文件第7页 
CD74HC7046A, CD74HCT7046A  
quency is lower than the COMP frequency, then it is the n- biased and the time constant in the path that charges the  
IN  
type driver that is held “ON” for most of the cycle. Subse- lock detector capacitor is T = (150Ω x C ).  
LD  
quently, the voltage at the capacitor (C2) of the low-pass filter  
During the fall time of the pulse the capacitor discharges  
through the 1.5kΩ and the 150Ω resistors and the channel  
resistance of the n-device of the NOR gate to ground  
connected to PC2  
varies until the signal and comparator  
OUT  
inputs are equal in both phase and frequency. At this stable  
point the voltage on C2 remains constant as the PC2 output is  
in three-state and the VCO input at pin 9 is a high impedance.  
(T = (1.5kΩ + 150Ω + Rn-channel) x C ).  
LD  
The waveform preset at the capacitor resembles a sawtooth  
as shown in Figure 7. The lock detector capacitor value is  
determined by the VCO center frequency. The typical range  
of capacitor for a frequency of 10MHz is about 10pF and for  
a frequency of 100kHz is about 1000pF. The chart in Figure  
8 can be used to select the proper lock detector capacitor  
value. As long as the loop remains locked and tracking, the  
level of the sawtooth will not go below the switching thresh-  
old of the Schmitt-trigger inverter. If the loop breaks lock, the  
width of the error pulse will be wide enough to allow the saw-  
tooth waveform to go below threshold and a level change at  
the output of the Schmitt trigger will indicate a loss of lock,  
as shown in Figure 9. The lock detector capacitor also acts  
to filter out small glitches that can occur when the loop is  
either seeking or losing lock.  
Thus, for PC2, no phase difference exists between SIG  
IN  
and COMP over the full frequency range of the VCO.  
IN  
Moreover, the power dissipation due to the low-pass filter is  
reduced because both p-type and n-type drivers are “OFF”  
for most of the signal input cycle. It should be noted that the  
PLL lock range for this type of phase comparator is equal to  
the capture range and is independent of the low-pass filter.  
With no signal present at SIG , the VCO adjusts, via PC2,  
IN  
to its lowest frequency.  
Lock Detector Theory of Operation  
Detection of a locked condition is accomplished by a NOR  
gate and an envelope detector as shown in Figure 6. When  
the PLL is in Lock, the output of the NOR gate is High and  
the lock detector output (Pin 1) is at a constant high level. As  
the loop tracks the signal on Pin 14 (signal in), the NOR gate  
outputs pulses whose widths represent the phase differ-  
ences between the VCO and the input signal. The time  
between pulses will be approximately equal to the time con-  
stant of the VCO center frequency. During the rise time of  
the pulse, the diode across the 1.5kΩ resistor is forward  
Note: When using phase comparator 1, the detector will only  
indicate a lock condition on the fundamental frequency and  
not on the harmonics, which PC1 will also lock on. If a detec-  
tion of lock is needed over the harmonic locking range of  
PC1, then the lock detector output must be OR-ed with the  
output of PC1.  
V
CC  
SIG  
IN  
V
DEMOUT (AV)  
COMP  
IN  
VCO  
OUT  
1/2 V  
CC  
PC1  
OUT  
V
CC  
VCO  
IN  
0
GND  
o
o
o
φDEMOUT  
0
90  
180  
FIGURE 2. PHASE COMPARATOR 1: AVERAGE OUTPUT  
VOLTAGE vs INPUT PHASE DIFFERENCE:  
FIGURE 3. TYPICAL WAVEFORMS FOR PLL USING PHASE  
COMPARATOR 1, LOOP LOCKED AT f  
o
V
= V  
= (V /π) (φSIGIN - φCOM-  
DEMOUT  
PC1OUT CC  
); φDEMOUT = (φSIGIN - φCOMPIN  
)
PIN  
4
1234567...26

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