Datasheet > 信号电路 > 锁相环或频率合成电路> CD74HCT7046AM96

CD74HCT7046AM96

更新时间： 2024-11-22 23:04:31

品牌	Logo	应用领域
德州仪器 - TI		信号电路锁相环或频率合成电路光电二极管
页数	文件大小	规格书
26页	301K
描述
Phase-Locked Loop with VCO and Lock Detector

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技术参数
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CD74HCT7046AM96 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	SOIC
包装说明：	SOP, SOP16,.25	针数：	16
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
Factory Lead Time：	1 week	风险等级：	0.75
模拟集成电路 - 其他类型：	PHASE LOCKED LOOP	JESD-30 代码：	R-PDSO-G16
JESD-609代码：	e4	长度：	9.9 mm
湿度敏感等级：	1	功能数量：	1
端子数量：	16	最高工作温度：	125 °C
最低工作温度：	-55 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装等效代码：	SOP16,.25
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	260	电源：	5 V
认证状态：	Not Qualified	座面最大高度：	1.58 mm
子类别：	PLL or Frequency Synthesis Circuits	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	MILITARY	端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	3.91 mm	Base Number Matches：	1

CD74HCT7046AM96 数据手册

CD74HC7046A,

CD74HCT7046A

Data sheet acquired from Harris Semiconductor

SCHS218C

Phase-Locked Loop

with VCO and Lock Detector

February 1998 - Revised October 2003

Features

Description

• Center Frequency of 18MHz (Typ) at V

Minimum Center Frequency of 12MHz at V

= 5V,

The CD74HC7046A and CD74HCT7046A high-speed

silicon-gate CMOS devices, speciﬁed in compliance with

JEDEC Standard No. 7A, are phase-locked-loop (PLL)

circuits that contain a linear voltage-controlled oscillator

(VCO), two-phase comparators (PC1, PC2), and a lock

detector. A signal input and a comparator input are common

to each comparator. The lock detector gives a HIGH level at

pin 1 (LD) when the PLL is locked. The lock detector

CC = 4.5V

[ /Title

(CD74

HC704

6A,

CD74

HCT70

46A)

• Choice of Two Phase Comparators

- Exclusive-OR

- Edge-Triggered JK Flip-Flop

• Excellent VCO Frequency Linearity

• VCO-Inhibit Control for ON/OFF Keying and for Low

Standby Power Consumption

capacitor must be connected between pin 15 (C ) and pin

8 (Gnd). For a frequency range of 100kHz to 10MHz, the

lock detector capacitor should be 1000pF to 10pF,

respectively.

• Minimal Frequency Drift

/Sub-

• Zero Voltage Offset Due to Op-Amp Buffer

ject

The signal input can be directly coupled to large voltage

signals, or indirectly coupled (with a series capacitor) to

small voltage signals. A self-bias input circuit keeps small

voltage signals within the linear region of the input ampliﬁers.

With a passive low-pass ﬁlter, the 7046A forms a second-

order loop PLL. The excellent VCO linearity is achieved by

the use of linear op-amp techniques.

• Operating Power-Supply Voltage Range

(Phase-

Locked

Loop

- VCO Section . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 6V

- Digital Section . . . . . . . . . . . . . . . . . . . . . . . . 2V to 6V

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55 C to 125 C

• Balanced Propagation Delay and Transition Times

Ordering Information

TEMP. RANGE

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

PART NUMBER

CD74HC7046AE

( C)

PACKAGE

16 Ld PDIP

-55 to 125

• HC Types

CD74HC7046AM

CD74HC7046AMT

CD74HC7046AM96

CD74HCT7046AE

CD74HCT7046AM

CD74HCT7046AMT

CD74HCT7046AM96

16 Ld SOIC

16 Ld PDIP

16 Ld SOIC

- 2V to 6V Operation

- High Noise Immunity: N = 30%, N = 30% of V

IL IH CC

at V

= 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V = 0.8V (Max), V = 2V (Min)

IL IH

- CMOS Input Compatibility, I ≤ 1µA at V , V

OL OH

NOTE: When ordering, use the entire part number. The sufﬁx 96

denotes tape and reel. The sufﬁx T denotes a small-quantity reel

of 250.

Applications

• FM Modulation and Demodulation

• Frequency Synthesis and Multiplication

• Frequency Discrimination

• Tone Decoding

• Data Synchronization and Conditioning

• Voltage-to-Frequency Conversion

• Motor-Speed Control

• Related Literature

- AN8823, CMOS Phase-Locked-Loop Application

Using the CD74HC/HCT7046A and

CD74HC/HCT7046A

0.1

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

12 3 4 5 6 7...26

中文翻译

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CD74HCT7046AM96 替代型号

型号	品牌	替代类型	描述	数据表
CD74HCT7046AMTG4	TI	完全替代	Phase-Locked Loop with VCO and Lock Detector
CD74HCT7046AMG4	TI	完全替代	Phase-Locked Loop with VCO and Lock Detector
CD74HCT7046AM96E4	TI	完全替代	Phase-Locked Loop with VCO and Lock Detector

与CD74HCT7046AM96相关器件

型号	品牌	获取价格	描述	数据表
CD74HCT7046AM96E4	TI	获取价格	Phase-Locked Loop with VCO and Lock Detector
CD74HCT7046AM96G4	TI	获取价格	Phase-Locked Loop with VCO and Lock Detector
CD74HCT7046AME4	TI	获取价格	Phase-Locked Loop with VCO and Lock Detector
CD74HCT7046AMG4	TI	获取价格	Phase-Locked Loop with VCO and Lock Detector
CD74HCT7046AMT	TI	获取价格	Phase-Locked Loop with VCO and Lock Detector
CD74HCT7046AMTE4	TI	获取价格	Phase-Locked Loop with VCO and Lock Detector
CD74HCT7046AMTG4	TI	获取价格	Phase-Locked Loop with VCO and Lock Detector
CD74HCT73	TI	获取价格	Dual J-K Flip-Flop with Reset Negative-Edge Trigger
CD74HCT73E	TI	获取价格	Dual J-K Flip-Flop with Reset Negative-Edge Trigger
CD74HCT73EE4	TI	获取价格	Dual J-K Flip-Flop with Reset Negative-Edge Trigger

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