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CD74HC125MG4 PDF预览

CD74HC125MG4

更新时间: 2024-11-01 14:49:39
品牌 Logo 应用领域
德州仪器 - TI 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
14页 437K
描述
High Speed CMOS Logic Quad Buffers with 3-State Outputs 14-SOIC -55 to 125

CD74HC125MG4 技术参数

是否Rohs认证:符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP14,.25
针数:14Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
Factory Lead Time:1 week风险等级:5.05
Is Samacsys:N其他特性:DUMMY VAL
控制类型:ENABLE LOW系列:HC/UH
JESD-30 代码:R-PDSO-G14JESD-609代码:e4
长度:8.65 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.006 A
湿度敏感等级:1位数:1
功能数量:4端口数量:2
端子数量:14最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP14,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TUBE峰值回流温度(摄氏度):260
电源:2/6 VProp。Delay @ Nom-Sup:30 ns
传播延迟(tpd):150 ns认证状态:Not Qualified
座面最大高度:1.75 mm子类别:Bus Driver/Transceiver
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):4.5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:3.9 mm
Base Number Matches:1

CD74HC125MG4 数据手册

 浏览型号CD74HC125MG4的Datasheet PDF文件第2页浏览型号CD74HC125MG4的Datasheet PDF文件第3页浏览型号CD74HC125MG4的Datasheet PDF文件第4页浏览型号CD74HC125MG4的Datasheet PDF文件第5页浏览型号CD74HC125MG4的Datasheet PDF文件第6页浏览型号CD74HC125MG4的Datasheet PDF文件第7页 
CD54HC125, CD74HC125,  
CD54HCT125, CD74HCT125  
Data sheet acquired from Harris Semiconductor  
SCHS143C  
High-Speed CMOS Logic  
Quad Buffer, Three-State  
November 1997 - Revised August 2003  
Features  
Description  
• Three-State Outputs  
The ’HC125 and ’HCT125 contain 4 independent three-state  
buffers, each having its own output enable input, which when  
“HIGH” puts the output in the high impedance state.  
• Separate Output Enable Inputs  
[ /Title  
(CD74  
HC125  
,
CD74  
HCT12  
5)  
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
Ordering Information  
o
o
TEMP. RANGE  
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
PART NUMBER  
CD54HC125F3A  
CD54HCT125F3A  
CD74HC125E  
( C)  
PACKAGE  
14 Ld CERDIP  
14 Ld CERDIP  
14 Ld PDIP  
14 Ld SOIC  
14 Ld SOIC  
14 Ld SOIC  
14 Ld PDIP  
14 Ld SOIC  
14 Ld SOIC  
14 Ld SOIC  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
/Sub-  
ject  
• HC Types  
- 2V to 6V Operation  
- High Noise Immunity: N = 30%, N = 30% of V  
CC  
(High  
Speed  
CMOS  
Logic  
Quad  
Buffer,  
Three-  
State)  
IL  
IH  
CD74HC125M  
at V  
= 5V  
CC  
CD74HC125MT  
CD74HC125M96  
CD74HCT125E  
CD74HCT125M  
CD74HCT125MT  
CD74HCT125M96  
• HCT Types  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
V = 0.8V (Max), V = 2V (Min)  
IL  
IH  
- CMOS Input Compatibility, I 1µA at V , V  
l
OL OH  
NOTE: When ordering, use the entire part number. The suffix 96  
denotes tape and reel. The suffix T denotes a small-quantity reel of  
250.  
Pinout  
CD54HC125, CD54HCT125  
(CERDIP)  
CD74HC125, CD74HCT125  
(PDIP, SOIC)  
TOP VIEW  
1OE  
1A  
1
2
3
4
5
6
7
14 V  
CC  
13 4OE  
12 4A  
1Y  
2OE  
2A  
11 4Y  
10 3OE  
2Y  
9
8
3A  
3Y  
GND  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2003, Texas Instruments Incorporated  
1

CD74HC125MG4 替代型号

型号 品牌 替代类型 描述 数据表
SN74HC125DR TI

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QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
CD74HC125M TI

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High Speed CMOS Logic Quad Buffer, Three-State
SN74HC125D TI

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QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS

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