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CD74HC126EE4 PDF预览

CD74HC126EE4

更新时间: 2024-11-01 05:18:11
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器逻辑集成电路光电二极管
页数 文件大小 规格书
14页 444K
描述
High-Speed CMOS Logic Quad Buffer, Three-State

CD74HC126EE4 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:DIP
包装说明:DIP, DIP14,.3针数:14
Reach Compliance Code:compliantHTS代码:8542.39.00.01
Factory Lead Time:1 week风险等级:5.1
控制类型:ENABLE HIGH系列:HC/UH
JESD-30 代码:R-PDIP-T14JESD-609代码:e4
长度:19.305 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.006 A
位数:1功能数量:4
端口数量:2端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP14,.3封装形状:RECTANGULAR
封装形式:IN-LINE包装方法:TUBE
峰值回流温度(摄氏度):NOT SPECIFIED电源:2/6 V
Prop。Delay @ Nom-Sup:30 ns传播延迟(tpd):150 ns
认证状态:Not Qualified座面最大高度:5.08 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):4.5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

CD74HC126EE4 数据手册

 浏览型号CD74HC126EE4的Datasheet PDF文件第2页浏览型号CD74HC126EE4的Datasheet PDF文件第3页浏览型号CD74HC126EE4的Datasheet PDF文件第4页浏览型号CD74HC126EE4的Datasheet PDF文件第5页浏览型号CD74HC126EE4的Datasheet PDF文件第6页浏览型号CD74HC126EE4的Datasheet PDF文件第7页 
CD54HC126, CD74HC126,  
CD54HCT126, CD74HCT126  
Data sheet acquired from Harris Semiconductor  
SCHS144C  
High-Speed CMOS Logic  
Quad Buffer, Three-State  
November 1997 - Revised September 2003  
Features  
Description  
• Three-State Outputs  
The ’HC126 and ’HCT126 contain four independent three-  
state buffers, each having its own output enable input, which  
when “low” puts the output in the high-impedance state.  
• Separate Output Enable Inputs  
[ /Title  
(CD74  
HC126  
,
CD74  
HCT12  
6)  
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
Ordering Information  
TEMP. RANGE  
o
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
PART NUMBER  
CD54HC126F3A  
CD54HCT126F3A  
CD74HC126E  
( C)  
PACKAGE  
14 Ld CERDIP  
14 Ld CERDIP  
14 Ld PDIP  
14 Ld SOIC  
14 Ld SOIC  
14 Ld SOIC  
14 Ld PDIP  
14 Ld SOIC  
14 Ld SOIC  
14 Ld SOIC  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
/Sub-  
ject  
• HC Types  
(High  
Speed  
CMOS  
Logic  
Quad  
Buffer,  
Three-  
State)  
- 2V to 6V Operation  
CD74HC126M  
- High Noise Immunity: N = 30%, N = 30% of V  
IL IH CC  
CD74HC126MT  
CD74HC126M96  
CD74HCT126E  
CD74HCT126M  
CD74HCT126MT  
CD74HCT126M96  
at V  
= 5V  
CC  
• HCT Types  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
V = 0.8V (Max), V = 2V (Min)  
IL IH  
- CMOS Input Compatibility, I 1µA at V , V  
OL OH  
l
NOTE: When ordering, use the entire part number. The suffix 96  
denotes tape and reel. The suffix T denotes a small-quantity reel of  
250.  
Pinout  
CD54HC126, CD54HC126  
(CERDIP)  
CD74HC126, CD74HC126  
(PDIP, SOIC)  
TOP VIEW  
1OE  
1A  
1
2
3
4
5
6
7
14 V  
CC  
13 4OE  
12 4A  
1Y  
2OE  
2A  
11 4Y  
10 3OE  
2Y  
9
8
3A  
3Y  
GND  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2003, Texas Instruments Incorporated  
1

CD74HC126EE4 替代型号

型号 品牌 替代类型 描述 数据表
SNJ54HC126J TI

完全替代

QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
CD74HC126E TI

完全替代

High Speed CMOS Logic Quad Buffer, Three-State
SN54HC126J TI

完全替代

QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS

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