CD74HC126,
CD74HCT126
Data sheet acquired from Harris Semiconductor
SCHS144
High Speed CMOS Logic
Quad Buffer, Three-State
November 1997
Features
Description
• Three-State Outputs
The Harris CD74HC126 and CD74HCT126 contain four
independent three-state buffers, each having its own output
enable input, which when “low” puts the output in the high-
impedance state.
• Separate Output Enable Inputs
[ /Title
(CD74
HC126
,
CD74
HCT12
6)
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads Ordering Information
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
TEMP. RANGE
PKG.
NO.
o
PART NUMBER
CD74HC126E
CD74HCT126E
CD74HC126M
CD74HCT126M
NOTES:
( C)
PACKAGE
14 Ld PDIP
14 Ld PDIP
14 Ld SOIC
14 Ld SOIC
-55 to 125
-55 to 125
-55 to 125
-55 to 125
E14.3
• Significant Power Reduction Compared to LSTTL
Logic ICs
/Sub-
ject
E14.3
• HC Types
M14.15
M14.15
(High
Speed
CMOS
Logic
Quad
Buffer,
Three-
State)
- 2V to 6V Operation
- High Noise Immunity: N = 30%, N = 30% of V
IL IH CC
at V
= 5V
CC
• HCT Types
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
- 4.5V to 5.5V Operation
2. Wafer and die for this part number is available which meets all
electrical specifications. Please contact your local sales office or
Harris customer service for ordering information.
- Direct LSTTL Input Logic Compatibility,
V = 0.8V (Max), V = 2V (Min)
IL IH
- CMOS Input Compatibility, I ≤ 1µA at V , V
OL OH
l
Pinout
CD74HC126, CD74HC126
(PDIP, SOIC)
TOP VIEW
1OE
1A
1
2
3
4
5
6
7
14 V
CC
13 4OE
12 4A
1Y
2OE
2A
11 4Y
10 3OE
2Y
9
8
3A
3Y
GND
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
File Number 1772.1
Copyright © Harris Corporation 1997
1