Datasheet > CD54HC195_06

CD54HC195_06

更新时间： 2024-09-16 05:09:03

品牌	Logo	应用领域
德州仪器 - TI		/
页数	文件大小	规格书
13页	341K
描述
High-Speed CMOS Logic 4-Bit Parallel Access Register

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CD54HC195_06 数据手册

CD54HC195, CD74HC195

Data sheet acquired from Harris Semiconductor

SCHS165E

High-Speed CMOS Logic

4-Bit Parallel Access Register

September 1997 - Revised October 2003

Features

Description

• Asynchronous Master Reset

• J, K, (D) Inputs to First Stage

• Fully Synchronous Serial or Parallel Data Transfer

• Shift Right and Parallel Load Capability

• Complementary Output From Last Stage

• Buffered Inputs

The device is useful in a wide variety of shifting, counting

and storage applications. It performs serial, parallel, serial to

parallel, or parallel to serial data transfers at very high

speeds.

[ /Title

(CD74

HC195

)

/Sub-

ject

(High

Speed

CMOS

Logic

4-Bit

Paral-

lel

The two modes of operation, shift right (Q -Q ) and parallel

load, are controlled by the state of the Parallel Enable (PE)

input. Serial data enters the ﬁrst ﬂip-ﬂop (Q ) via the J and K

inputs when the PE input is high, and is shifted one bit in the

direction Q -Q -Q -Q following each Low to High clock

• Typical f

MAX

= 50MHz at V = 5V,

transition. The J and K inputs provide the ﬂexibility of the JK-

type input for special applications and by tying the two pins

together, the simple D-type input for general applications.

The device appears as four common-clocked D ﬂip-ﬂops

when the PE input is Low. After the Low to High clock

transition, data on the parallel inputs (D0-D3) is transferred

to the respective Q -Q outputs. Shift left operation (Q -Q )

C = 15pF, T = 25 C

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55 C to 125 C

• Balanced Propagation Delay and Transition Times

can be achieved by tying the Q outputs to the Dn-1 inputs

and holding the PE input low.

Access

Regis-

ter)

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

All parallel and serial data transfers are synchronous, occurring

after each Low to High clock transition. The ’HC195 series

utilizes edge triggering; therefore, there is no restriction on the

activity of the J, K, Pn and PE inputs for logic operations, other

than set-up and hold time requirements. A Low on the

asynchronous Master Reset (MR) input sets all Q outputs Low,

independent of any other input condition.

• HC Types

/Autho

- 2V to 6V Operation

- High Noise Immunity: N = 30%, N = 30%of V

= 5V

Ordering Information

PInout

TEMP. RANGE

PART NUMBER

CD54HC195F3A

CD74HC195E

( C)

PACKAGE

16 Ld CERDIP

16 Ld PDIP

CD54HC195

(CERDIP)

CD74HC195

-55 to 125

(PDIP, SOIC, SOP, TSSOP)

TOP VIEW

CD74HC195M

16 Ld SOIC

16 V

CD74HC195NSR

CD74HC195PW

CD74HC195PWR

CD74HC195PWT

16 Ld SOP

15 Q

14 Q

13 Q

12 Q

11 Q

16 Ld TSSOP

GND

NOTE: When ordering, use the entire part number. The sufﬁx R

denotes tape and reel. The sufﬁx T denotes a small-quantity reel of

250.

10 CP

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

12 3 4 5 6 7...13

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与CD54HC195_06相关器件

型号	品牌	获取价格	描述	数据表
CD54HC195_08	TI	获取价格	High-Speed CMOS Logic 4-Bit Parallel Access Register
CD54HC195E	ETC	获取价格	Logic IC
CD54HC195EN	ETC	获取价格	Logic IC
CD54HC195F	ETC	获取价格	Logic IC
CD54HC195F/3	RENESAS	获取价格	Parallel In Parallel Out, HC/UH Series, 4-Bit, Right Direction, True Output, CMOS, CDIP16
CD54HC195F3A	TI	获取价格	High-Speed CMOS Logic 4-Bit Parallel Access Register
CD54HC195F3A	ROCHESTER	获取价格	Parallel In Parallel Out, HC/UH Series, 4-Bit, Right Direction, True Output, CMOS, CDIP16
CD54HC195H	RENESAS	获取价格	CD54HC195H
CD54HC195H/3	RENESAS	获取价格	HC/UH SERIES, 4-BIT RIGHT PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, UUC16
CD54HC195H/3A	RENESAS	获取价格	HC/UH SERIES, 4-BIT RIGHT PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, UUC16

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