CD54HC125, CD74HC125,
CD54HCT125, CD74HCT125
Data sheet acquired from Harris Semiconductor
SCHS143C
High-Speed CMOS Logic
Quad Buffer, Three-State
November 1997 - Revised August 2003
Features
Description
• Three-State Outputs
The ’HC125 and ’HCT125 contain 4 independent three-state
buffers, each having its own output enable input, which when
“HIGH” puts the output in the high impedance state.
• Separate Output Enable Inputs
[ /Title
(CD74
HC125
,
CD74
HCT12
5)
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
Ordering Information
o
o
TEMP. RANGE
o
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
PART NUMBER
CD54HC125F3A
CD54HCT125F3A
CD74HC125E
( C)
PACKAGE
14 Ld CERDIP
14 Ld CERDIP
14 Ld PDIP
14 Ld SOIC
14 Ld SOIC
14 Ld SOIC
14 Ld PDIP
14 Ld SOIC
14 Ld SOIC
14 Ld SOIC
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
• Significant Power Reduction Compared to LSTTL
Logic ICs
/Sub-
ject
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N = 30%, N = 30% of V
CC
(High
Speed
CMOS
Logic
Quad
Buffer,
Three-
State)
IL
IH
CD74HC125M
at V
= 5V
CC
CD74HC125MT
CD74HC125M96
CD74HCT125E
CD74HCT125M
CD74HCT125MT
CD74HCT125M96
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V = 0.8V (Max), V = 2V (Min)
IL
IH
- CMOS Input Compatibility, I ≤ 1µA at V , V
l
OL OH
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel of
250.
Pinout
CD54HC125, CD54HCT125
(CERDIP)
CD74HC125, CD74HCT125
(PDIP, SOIC)
TOP VIEW
1OE
1A
1
2
3
4
5
6
7
14 V
CC
13 4OE
12 4A
1Y
2OE
2A
11 4Y
10 3OE
2Y
9
8
3A
3Y
GND
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1