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CD54HC125F3A PDF预览

CD54HC125F3A

更新时间: 2024-11-22 22:34:27
品牌 Logo 应用领域
德州仪器 - TI 逻辑集成电路驱动
页数 文件大小 规格书
11页 269K
描述
High-Speed CMOS Logic Quad Buffer, Three-State

CD54HC125F3A 技术参数

生命周期:Active零件包装代码:DIP
包装说明:DIP, DIP14,.3针数:14
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:6 weeks
风险等级:5.18其他特性:DUMMY VAL
控制类型:ENABLE LOW计数方向:UNIDIRECTIONAL
系列:HC/UHJESD-30 代码:R-GDIP-T14
长度:19.56 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.006 A
位数:1功能数量:4
端口数量:2端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装等效代码:DIP14,.3封装形状:RECTANGULAR
封装形式:IN-LINE包装方法:TUBE
峰值回流温度(摄氏度):NOT SPECIFIED电源:2/6 V
Prop。Delay @ Nom-Sup:30 ns传播延迟(tpd):150 ns
认证状态:Not Qualified筛选级别:38535Q/M;38534H;883B
座面最大高度:5.08 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):4.5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:6.67 mmBase Number Matches:1

CD54HC125F3A 数据手册

 浏览型号CD54HC125F3A的Datasheet PDF文件第2页浏览型号CD54HC125F3A的Datasheet PDF文件第3页浏览型号CD54HC125F3A的Datasheet PDF文件第4页浏览型号CD54HC125F3A的Datasheet PDF文件第5页浏览型号CD54HC125F3A的Datasheet PDF文件第6页浏览型号CD54HC125F3A的Datasheet PDF文件第7页 
CD54HC125, CD74HC125,  
CD54HCT125, CD74HCT125  
Data sheet acquired from Harris Semiconductor  
SCHS143C  
High-Speed CMOS Logic  
Quad Buffer, Three-State  
November 1997 - Revised August 2003  
Features  
Description  
• Three-State Outputs  
The ’HC125 and ’HCT125 contain 4 independent three-state  
buffers, each having its own output enable input, which when  
“HIGH” puts the output in the high impedance state.  
• Separate Output Enable Inputs  
[ /Title  
(CD74  
HC125  
,
CD74  
HCT12  
5)  
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
Ordering Information  
o
o
TEMP. RANGE  
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
PART NUMBER  
CD54HC125F3A  
CD54HCT125F3A  
CD74HC125E  
( C)  
PACKAGE  
14 Ld CERDIP  
14 Ld CERDIP  
14 Ld PDIP  
14 Ld SOIC  
14 Ld SOIC  
14 Ld SOIC  
14 Ld PDIP  
14 Ld SOIC  
14 Ld SOIC  
14 Ld SOIC  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
/Sub-  
ject  
• HC Types  
- 2V to 6V Operation  
- High Noise Immunity: N = 30%, N = 30% of V  
CC  
(High  
Speed  
CMOS  
Logic  
Quad  
Buffer,  
Three-  
State)  
IL  
IH  
CD74HC125M  
at V  
= 5V  
CC  
CD74HC125MT  
CD74HC125M96  
CD74HCT125E  
CD74HCT125M  
CD74HCT125MT  
CD74HCT125M96  
• HCT Types  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
V = 0.8V (Max), V = 2V (Min)  
IL  
IH  
- CMOS Input Compatibility, I 1µA at V , V  
l
OL OH  
NOTE: When ordering, use the entire part number. The suffix 96  
denotes tape and reel. The suffix T denotes a small-quantity reel of  
250.  
Pinout  
CD54HC125, CD54HCT125  
(CERDIP)  
CD74HC125, CD74HCT125  
(PDIP, SOIC)  
TOP VIEW  
1OE  
1A  
1
2
3
4
5
6
7
14 V  
CC  
13 4OE  
12 4A  
1Y  
2OE  
2A  
11 4Y  
10 3OE  
2Y  
9
8
3A  
3Y  
GND  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2003, Texas Instruments Incorporated  
1

CD54HC125F3A 替代型号

型号 品牌 替代类型 描述 数据表
SNJ54HC125J TI

完全替代

QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
CD74HCT125E TI

完全替代

High Speed CMOS Logic Quad Buffer, Three-State
SN54HC125J TI

完全替代

QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS

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