CD54HC126, CD74HC126,
CD54HCT126, CD74HCT126
Data sheet acquired from Harris Semiconductor
SCHS144C
High-Speed CMOS Logic
Quad Buffer, Three-State
November 1997 - Revised September 2003
Features
Description
• Three-State Outputs
The ’HC126 and ’HCT126 contain four independent three-
state buffers, each having its own output enable input, which
when “low” puts the output in the high-impedance state.
• Separate Output Enable Inputs
[ /Title
(CD74
HC126
,
CD74
HCT12
6)
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
Ordering Information
TEMP. RANGE
o
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C
• Balanced Propagation Delay and Transition Times
PART NUMBER
CD54HC126F3A
CD54HCT126F3A
CD74HC126E
( C)
PACKAGE
14 Ld CERDIP
14 Ld CERDIP
14 Ld PDIP
14 Ld SOIC
14 Ld SOIC
14 Ld SOIC
14 Ld PDIP
14 Ld SOIC
14 Ld SOIC
14 Ld SOIC
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
• Significant Power Reduction Compared to LSTTL
Logic ICs
/Sub-
ject
• HC Types
(High
Speed
CMOS
Logic
Quad
Buffer,
Three-
State)
- 2V to 6V Operation
CD74HC126M
- High Noise Immunity: N = 30%, N = 30% of V
IL IH CC
CD74HC126MT
CD74HC126M96
CD74HCT126E
CD74HCT126M
CD74HCT126MT
CD74HCT126M96
at V
= 5V
CC
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V = 0.8V (Max), V = 2V (Min)
IL IH
- CMOS Input Compatibility, I ≤ 1µA at V , V
OL OH
l
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel of
250.
Pinout
CD54HC126, CD54HC126
(CERDIP)
CD74HC126, CD74HC126
(PDIP, SOIC)
TOP VIEW
1OE
1A
1
2
3
4
5
6
7
14 V
CC
13 4OE
12 4A
1Y
2OE
2A
11 4Y
10 3OE
2Y
9
8
3A
3Y
GND
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
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