生命周期: | Active | 零件包装代码: | DIP |
包装说明: | DIP, DIP14,.3 | 针数: | 14 |
Reach Compliance Code: | not_compliant | ECCN代码: | EAR99 |
HTS代码: | 8542.39.00.01 | 风险等级: | 5.2 |
系列: | HC/UH | JESD-30 代码: | R-GDIP-T14 |
长度: | 19.56 mm | 负载电容(CL): | 50 pF |
逻辑集成电路类型: | NAND GATE | 最大I(ol): | 0.0052 A |
功能数量: | 3 | 输入次数: | 3 |
端子数量: | 14 | 最高工作温度: | 125 °C |
最低工作温度: | -55 °C | 封装主体材料: | CERAMIC, GLASS-SEALED |
封装代码: | DIP | 封装等效代码: | DIP14,.3 |
封装形状: | RECTANGULAR | 封装形式: | IN-LINE |
包装方法: | TUBE | 峰值回流温度(摄氏度): | NOT SPECIFIED |
电源: | 2/6 V | 最大电源电流(ICC): | 0.04 mA |
Prop。Delay @ Nom-Sup: | 30 ns | 传播延迟(tpd): | 150 ns |
认证状态: | Not Qualified | 施密特触发器: | NO |
筛选级别: | 38535Q/M;38534H;883B | 座面最大高度: | 5.08 mm |
子类别: | Gates | 最大供电电压 (Vsup): | 6 V |
最小供电电压 (Vsup): | 2 V | 标称供电电压 (Vsup): | 4.5 V |
表面贴装: | NO | 技术: | CMOS |
温度等级: | MILITARY | 端子形式: | THROUGH-HOLE |
端子节距: | 2.54 mm | 端子位置: | DUAL |
处于峰值回流温度下的最长时间: | NOT SPECIFIED | 宽度: | 6.67 mm |
Base Number Matches: | 1 |
型号 | 品牌 | 替代类型 | 描述 | 数据表 |
CD74HC10E | TI |
完全替代 |
High-Speed CMOS Logic Triple 3-Input NAND Gate | |
SN74HC10NE4 | TI |
类似代替 |
TRIPLE 3-INPUT POSITIVE-NAND GATES | |
SN74HC10N | TI |
类似代替 |
TRIPLE 3-INPUT POSITIVE-NAND GATES |
型号 | 品牌 | 获取价格 | 描述 | 数据表 |
CD54HC10H/3 | RENESAS |
获取价格 |
HC/UH SERIES, TRIPLE 3-INPUT NAND GATE, UUC14 | |
CD54HC10H/3A | RENESAS |
获取价格 |
NAND Gate, HC/UH Series, 3-Func, 3-Input, CMOS | |
CD54HC11 | TI |
获取价格 |
High Speed CMOS Logic Triple 3-Input AND Gate | |
CD54HC11_06 | TI |
获取价格 |
High-Speed CMOS Logic Triple 3-Input AND Gate | |
CD54HC11_08 | TI |
获取价格 |
High-Speed CMOS Logic Triple 3-Input AND Gate | |
CD54HC11_14 | TI |
获取价格 |
High-Speed CMOS Logic Triple 3-Input AND Gate | |
CD54HC112 | TI |
获取价格 |
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger | |
CD54HC112_08 | TI |
获取价格 |
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger | |
CD54HC112_15 | TI |
获取价格 |
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger | |
CD54HC112E | ETC |
获取价格 |
Logic IC |