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CD54HC10F3A PDF预览

CD54HC10F3A

更新时间: 2024-02-28 16:27:18
品牌 Logo 应用领域
德州仪器 - TI
页数 文件大小 规格书
10页 265K
描述
High-Speed CMOS Logic Triple 3-Input NAND Gate

CD54HC10F3A 技术参数

生命周期:Active零件包装代码:DIP
包装说明:DIP, DIP14,.3针数:14
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.2
系列:HC/UHJESD-30 代码:R-GDIP-T14
长度:19.56 mm负载电容(CL):50 pF
逻辑集成电路类型:NAND GATE最大I(ol):0.0052 A
功能数量:3输入次数:3
端子数量:14最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DIP封装等效代码:DIP14,.3
封装形状:RECTANGULAR封装形式:IN-LINE
包装方法:TUBE峰值回流温度(摄氏度):NOT SPECIFIED
电源:2/6 V最大电源电流(ICC):0.04 mA
Prop。Delay @ Nom-Sup:30 ns传播延迟(tpd):150 ns
认证状态:Not Qualified施密特触发器:NO
筛选级别:38535Q/M;38534H;883B座面最大高度:5.08 mm
子类别:Gates最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):4.5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:6.67 mm
Base Number Matches:1

CD54HC10F3A 数据手册

 浏览型号CD54HC10F3A的Datasheet PDF文件第2页浏览型号CD54HC10F3A的Datasheet PDF文件第3页浏览型号CD54HC10F3A的Datasheet PDF文件第4页浏览型号CD54HC10F3A的Datasheet PDF文件第5页浏览型号CD54HC10F3A的Datasheet PDF文件第6页浏览型号CD54HC10F3A的Datasheet PDF文件第7页 
CD54HC10, CD74HC10,  
CD54HCT10, CD74HCT10  
Data sheet acquired from Harris Semiconductor  
SCHS128C  
High-Speed CMOS Logic  
Triple 3-Input NAND Gate  
August 1997 - Revised September 2003  
Features  
Description  
[ /Title  
(CD74  
HC10,  
CD74  
HCT10  
)
• Buffered Inputs  
The ’HC10 and ’HCT10 logic gates utilize silicon gate CMOS  
technology to achieve operating speeds similar to LSTTL  
gates with the low power consumption of standard CMOS  
integrated circuits. All devices have the ability to drive 10  
LSTTL loads. The HCT logic family is functionally pin  
compatible with the standard LS logic family.  
• Typical Propagation Delay: 8ns at V  
o
= 5V,  
CC  
C = 15pF, T = 25 C  
L
A
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
/Sub-  
ject  
Ordering Information  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
TEMP. RANGE  
o
(High  
Speed  
CMOS  
Logic  
Triple  
3-Input  
NAND  
Gate)  
/Autho  
r ()  
/Key-  
words  
(High  
Speed  
CMOS  
Logic  
Triple  
3-Input  
NAND  
Gate,  
PART NUMBER  
CD54HC10F3A  
( C)  
PACKAGE  
14 Ld CERDIP  
14 Ld CERDIP  
14 Ld PDIP  
14 Ld SOIC  
14 Ld SOIC  
14 Ld SOIC  
14 Ld PDIP  
14 Ld SOIC  
14 Ld SOIC  
14 Ld SOIC  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
-55 to 125  
CD54HCT10F3A  
CD74HC10E  
• HC Types  
- 2V to 6V Operation  
- High Noise Immunity: N = 30%, N = 30% of V  
IL IH CC  
CD74HC10M  
at V  
= 5V  
CC  
CD74HC10MT  
CD74HC10M96  
CD74HCT10E  
CD74HCT10M  
CD74HCT10MT  
CD74HCT10M96  
• HCT Types  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
V = 0.8V (Max), V = 2V (Min)  
IL  
IH  
- CMOS Input Compatibility, I 1µA at V , V  
OL OH  
l
NOTE: When ordering, use the entire part number. The suffix 96  
denotes tape and reel. The suffix T denotes a small-quantity reel  
of 250.  
Pinout  
CD54HC10, CD54HCT10  
(CERDIP)  
High  
Speed  
CMOS  
Logic  
Triple  
3-Input  
NAND  
Gate,  
CD74HC10, CD74HCT10  
(PDIP, SOIC)  
TOP VIEW  
1A  
1B  
1
2
3
4
5
6
7
14 V  
CC  
13 1C  
12 1Y  
11 3C  
10 3B  
2A  
2B  
Harris  
Semi-  
2C  
2Y  
9
8
3A  
3Y  
GND  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2003, Texas Instruments Incorporated  
1

CD54HC10F3A 替代型号

型号 品牌 替代类型 描述 数据表
CD74HC10E TI

完全替代

High-Speed CMOS Logic Triple 3-Input NAND Gate
SN74HC10NE4 TI

类似代替

TRIPLE 3-INPUT POSITIVE-NAND GATES
SN74HC10N TI

类似代替

TRIPLE 3-INPUT POSITIVE-NAND GATES

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