Datasheet > CD54HC112

CD54HC112

更新时间： 2024-11-01 00:00:55

品牌	Logo	应用领域
德州仪器 - TI		触发器
页数	文件大小	规格书
13页	346K
描述
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger

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数据手册
替代型号

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CD54HC112 数据手册

CD54HC112, CD74HC112,

CD54HCT112, CD74HCT112

Data sheet acquired from Harris Semiconductor

SCHS141H

Dual J-K Flip-Flop with Set and Reset

Negative-Edge Trigger

March 1998 - Revised October 2003

Features

Description

• Hysteresis on Clock Inputs for Improved Noise

Immunity and Increased Input Rise and Fall Times

The ’HC112 and ’HCT112 utilize silicon-gate CMOS

technology to achieve operating speeds equivalent to LSTTL

parts. They exhibit the low power consumption of standard

CMOS integrated circuits, together with the ability to drive 10

LSTTL loads.

[ /Title

(CD74

HC112

CD74

HCT11

• Asynchronous Set and Reset

• Complementary Outputs

• Buffered Inputs

These ﬂip-ﬂops have independent J, K, Set, Reset, and

Clock inputs and Q and Q outputs. They change state on the

negative-going transition of the clock pulse. Set and Reset

are accomplished asynchronously by low-level inputs.

• Typical f

MAX

= 60MHz at V = 5V, C = 15pF,

CC L

T = 25 C

• Fanout (Over Temperature Range)

The HCT logic family is functionally as well as pin-

compatible with the standard LS logic family.

/Sub-

ject

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

(Dual

J-K

Flip-

Flop

• Wide Operating Temperature Range . . . -55 C to 125 C

• Balanced Propagation Delay and Transition Times

Ordering Information

TEMP. RANGE

PART NUMBER

CD54HC112F3A

CD54HCT112F3A

CD74HC112E

( C)

PACKAGE

16 Ld CERDIP

16 Ld PDIP

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

-55 to 125

with

• HC Types

Setand

Reset

Nega-

- 2V to 6V Operation

- High Noise Immunity: N = 30%, N = 30% of V

IL IH CC

CD74HC112MT

CD74HC112M96

CD74HC112NSR

CD74HC112PW

CD74HC112PWR

CD74HC112PWT

CD74HCT112E

16 Ld SOIC

at V

= 5V

16 Ld SOIC

• HCT Types

16 Ld SOP

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

16 Ld TSSOP

16 Ld PDIP

V = 0.8V (Max), V = 2V (Min)

IL IH

- CMOS Input Compatibility, I ≤ 1µA at V , V

OL OH

Pinout

NOTE: When ordering, use the entire part number. The sufﬁxes 96

and R denote tape and reel. The sufﬁx T denotes a small-quantity

reel of 250.

CD54HC112, CD54HCT112 (CERDIP)

CD74HC112 (PDIP, SOIC, SOP, TSSOP)

CD74HCT112 (PDIP)

TOP VIEW

1CP

16 V

15 1R

14 2R

13 2CP

12 2K

11 2J

10 2S

GND

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

12 3 4 5 6 7...13

中文翻译

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CD54HC112 替代型号

型号	品牌	替代类型	描述	数据表
CD74HC112	TI	功能相似	Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger

与CD54HC112相关器件

型号	品牌	获取价格	描述	数据表
CD54HC112_08	TI	获取价格	Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger
CD54HC112_15	TI	获取价格	Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger
CD54HC112E	ETC	获取价格	Logic IC
CD54HC112EN	ETC	获取价格	Logic IC
CD54HC112F	RENESAS	获取价格	IC,FLIP-FLOP,DUAL,J/K TYPE,HC-CMOS,DIP,16PIN,CERAMIC
CD54HC112F/3	RENESAS	获取价格	HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP16
CD54HC112F/3A	RENESAS	获取价格	IC HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP16,
CD54HC112F3A	TI	获取价格	Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger
CD54HC112F3A	RENESAS	获取价格	HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP16
CD54HC112H	ETC	获取价格	Logic IC

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