Datasheet > CD54HC11_14

CD54HC11_14

更新时间： 2024-11-02 02:58:43

品牌	Logo	应用领域
德州仪器 - TI		栅
页数	文件大小	规格书
6页	36K
描述
High-Speed CMOS Logic Triple 3-Input AND Gate

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数据手册

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CD54HC11_14 数据手册

CD54/74HC11,

CD54/74HCT11

Data sheet acquired from Harris Semiconductor

SCHS273A

High Speed CMOS Logic

Triple 3-Input AND Gate

August 1997 - Revised May 2000

Features

Description

• Buffered Inputs

The ’HC11 and ’HCT11 logic gates utilize silicon gate CMOS

technology to achieve operating speeds similar to LSTTL

gates with the low power consumption of standard CMOS

integrated circuits. All devices have the ability to drive 10

LSTTL loads. The HCT logic family is functionally pin

compatible with the standard LS logic family.

• Typical Propagation Delay: 8ns at V

= 5V,

[ /Title

(CD54

HCT11

CD74

HC11,

CD74

HCT11

)

C = 15pF, T = 25 C

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

Ordering Information

• Wide Operating Temperature Range . . . -55 C to 125 C

• Balanced Propagation Delay and Transition Times

TEMP. RANGE

PART NUMBER

CD54HC11F

( C)

PACKAGE

14 Ld CERDIP

14 Ld PDIP

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

-55 to 125

/Sub-

ject

(High

CD54HC11F3A

CD74HC11E

CD74HC11M

CD54HCT11F

CD54HCT11F3A

CD74HCT11E

CD74HCT11M

NOTES:

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N = 30%, N = 30% of V

IL IH CC

14 Ld SOIC

at V

= 5V

14 Ld CERDIP

14 Ld PDIP

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V = 0.8V (Max), V = 2V (Min)

IL IH

14 Ld SOIC

- CMOS Input Compatibility, I ≤ 1µA at V , V

OL OH

1. When ordering, use the entire part number. Add the sufﬁx 96 to

obtain the variant in the tape and reel.

2. Die for this part number is available which meets all electrical

specifications. Please contact your local TI sales office or cus-

tomer service for ordering information.

Pinout

CD54HC11, CD54HCT11

(CERDIP)

CD54HCT11, CD74HC11, CD74HCT11

(PDIP, SOIC)

TOP VIEW

14 V

13 1C

12 1Y

11 3C

10 3B

GND

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

12 3 4 5 6

中文翻译

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与CD54HC11_14相关器件

型号	品牌	获取价格	描述	数据表
CD54HC112	TI	获取价格	Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger
CD54HC112_08	TI	获取价格	Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger
CD54HC112_15	TI	获取价格	Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger
CD54HC112E	ETC	获取价格	Logic IC
CD54HC112EN	ETC	获取价格	Logic IC
CD54HC112F	RENESAS	获取价格	IC,FLIP-FLOP,DUAL,J/K TYPE,HC-CMOS,DIP,16PIN,CERAMIC
CD54HC112F/3	RENESAS	获取价格	HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP16
CD54HC112F/3A	RENESAS	获取价格	IC HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP16,
CD54HC112F3A	TI	获取价格	Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger
CD54HC112F3A	RENESAS	获取价格	HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP16

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