Datasheet > CD54AC112_06

CD54AC112_06

更新时间： 2024-09-15 05:08:59

品牌	Logo	应用领域
德州仪器 - TI		触发器
页数	文件大小	规格书
11页	336K
描述
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

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CD54AC112_06 数据手册

CD54AC112, CD74AC112

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS

WITH CLEAR AND PRESET

SCHS325 – JANUARY 2003

CD54AC112 . . . F PACKAGE

CD74AC112 . . . E OR M PACKAGE

(TOP VIEW)

AC Types Feature 1.5-V to 5.5-V Operation

and Balanced Noise Immunity at 30% of the

Supply Voltage

Speed of Bipolar F, AS, and S, With

Significantly Reduced Power Consumption

1CLK

1CLR

2CLR

2CLK

Balanced Propagation Delays

1PRE

±24-mA Output Drive Current

– Fanout to 15 F Devices

11 2J

SCR-Latchup-Resistant CMOS Process and

Circuit Design

2PRE

GND

Exceeds 2-kV ESD Protection Per

MIL-STD-883, Method 3015

description/ordering information

The ’AC112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset

(PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE

and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements is transferred to

the outputs on the negative-going edge of the clock pulse (CLK). Clock triggering occurs at a voltage level and

is not directly related to the fall time of the clock pulse. Following the hold-time interval, data at the J and K inputs

may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle

flip-flops by tying J and K high.

ORDERING INFORMATION

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

†

PACKAGE

PDIP – E

SOIC – M

CDIP – F

Tube

CD74AC112E

CD74AC112M

CD74AC112E

–55°C to 125°C

AC112M

Tape and reel CD74AC112M96

Tube CD54AC112F3A

CD54AC112F3A

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines

are available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

On products compliant to MIL-PRF-38535, all parameters are tested

unless otherwise noted. On all other products, production

processing does not necessarily include testing of all parameters.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...11

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与CD54AC112_06相关器件

型号	品牌	获取价格	描述	数据表
CD54AC112_14	TI	获取价格	DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS
CD54AC112E	ETC	获取价格	Logic IC
CD54AC112EN	ETC	获取价格	Logic IC
CD54AC112F	ETC	获取价格	Logic IC
CD54AC112F3A	TI	获取价格	DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
CD54AC112H	ETC	获取价格	Logic IC
CD54AC112HX	GE	获取价格	J-K Flip-Flop, AC Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CM
CD54AC112M	ETC	获取价格	Logic IC
CD54AC113A	INTERSIL	获取价格	Dual “J-K” Flip-Flop with Set and Reset
CD54AC138	TI	获取价格	3-to-8-Line Decoders/Demultiplexers

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