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CD4538BMD PDF预览

CD4538BMD

更新时间: 2024-11-04 13:06:43
品牌 Logo 应用领域
美国国家半导体 - NSC /
页数 文件大小 规格书
10页 239K
描述
IC,MONOSTABLE MULTIVIBRATOR,CMOS,DIP,16PIN,CERAMIC

CD4538BMD 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP16,.3Reach Compliance Code:unknown
风险等级:5.92系列:4000/14000/40000
JESD-30 代码:R-CDIP-T16JESD-609代码:e0
逻辑集成电路类型:MONOSTABLE MULTIVIBRATOR数据/时钟输入次数:2
功能数量:2端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
输出极性:COMPLEMENTARY封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:DIP封装等效代码:DIP16,.3
封装形状:RECTANGULAR封装形式:IN-LINE
电源:5/15 V传播延迟(tpd):600 ns
认证状态:Not Qualified子类别:Prescaler/Multivibrators
最大供电电压 (Vsup):15 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
Base Number Matches:1

CD4538BMD 数据手册

 浏览型号CD4538BMD的Datasheet PDF文件第2页浏览型号CD4538BMD的Datasheet PDF文件第3页浏览型号CD4538BMD的Datasheet PDF文件第4页浏览型号CD4538BMD的Datasheet PDF文件第5页浏览型号CD4538BMD的Datasheet PDF文件第6页浏览型号CD4538BMD的Datasheet PDF文件第7页 
February 1988  
CD4538BM/CD4538BC Dual Precision Monostable  
General Description  
Features  
Y
Wide supply voltage range  
3.0V to 15V  
0.45 V (typ.)  
The CD4538B is a dual, precision monostable multivibrator  
with independent trigger and reset controls. The device is  
retriggerable and resettable, and the control inputs are inter-  
nally latched. Two trigger inputs are provided to allow either  
rising or falling edge triggering. The reset inputs are active  
low and prevent triggering while active. Precise control of  
output pulse-width has been achieved using linear CMOS  
techniques. The pulse duration and accuracy are deter-  
Y
High noise immunity  
CC  
Y
Low power  
TTL compatibility  
Fan out of 2 driving 74L  
or 1 driving 74LS  
Y
e
New formula: PW  
(PW in seconds, R in Ohms, C in Farads)  
RC  
OUT  
Y
Y
Y
Y
Y
g
Wide pulse-width range  
1.0% pulse-width variation from part to part (typ.)  
%
1 ms to  
mined by external components R and C . The device does  
X
X
Separate latched reset inputs  
Symmetrical output sink and source capability  
Low standby current  
not allow the timing capacitor to discharge through the tim-  
ing pin on power-down condition. For this reason, no exter-  
nal protection resistor is required in series with the timing  
pin. Input protection from static discharge is provided on all  
pins.  
5 nA (typ.)  
@
5 V  
DC  
Y
Pin compatible to CD4528B  
Block and Connection Diagrams  
Dual-In-Line Package  
CD4538BM  
CD4538BC  
TL/F/6000–2  
Top View  
Order Number CD4538B  
TL/F/6000–1  
R
and C are External Components  
X
X
e
e
V
Pin 16  
Pin 8  
DD  
V
SS  
Truth Table  
e
e
e
e
e
e
e
H
High Level  
Inputs  
Outputs  
L
Low Level  
Transition from Low to High  
Transition from High to Low  
One High Level Pulse  
One Low Level Pulse  
Irrelevant  
u
v
É
ß
X
Clear  
A
B
Q
Q
L
X
X
H
H
X
H
X
X
X
L
L
H
H
L
L
H
L
É
É
ß
ß
v
H
u
C
1995 National Semiconductor Corporation  
TL/F/6000  
RRD-B30M105/Printed in U. S. A.  

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