CD4541BCM

更新时间： 2024-02-15 13:12:26

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		计数器逻辑集成电路光电二极管 PC
页数	文件大小	规格书
8页	80K
描述
Programmable Timer

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技术参数
数据手册

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CD4541BCM 技术参数

生命周期：	Obsolete	零件包装代码：	TSSOP
包装说明：	TSSOP, TSSOP14,.25	针数：	14
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.24	计数方向：	UP
系列：	4000/14000/40000	JESD-30 代码：	R-PDSO-G14
长度：	5 mm	负载/预设输入：	YES
逻辑集成电路类型：	BINARY COUNTER	工作模式：	SYNCHRONOUS
位数：	16	功能数量：	1
端子数量：	14	最高工作温度：	125 °C
最低工作温度：	-55 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP	封装等效代码：	TSSOP14,.25
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
传播延迟（tpd）：	10.5 ns	认证状态：	Not Qualified
座面最大高度：	1.2 mm	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	MILITARY	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	DUAL
触发器类型：	POSITIVE EDGE	宽度：	4.4 mm

CD4541BCM 数据手册

October 1987

Revised March 1999

CD4541BC

Programmable Timer

■ Oscillator frequency range ≈ DC to 100 kHz

General Description

■ Oscillator may be bypassed if external clock is available

(apply external clock to pin 3)

The CD4541BC Programmable Timer is designed with a

16-stage binary counter, an integrated oscillator for use

with an external capacitor and two resistors, output control

logic, and a special power-on reset circuit. The special fea-

tures of the power-on reset circuit are first, no additional

static power consumption and second, the part functions

across the full voltage range (3V–15V) whether power-on

reset is enabled or disabled.

■ Automatic reset initializes all counters when power turns

■ External master reset totally independent of automatic

reset operation

■ Operates at 2ⁿfrequency divider or single transition

timer

Timing and the counter are initialized by turning on power,

if the power-on reset is enabled. When the power is

already on, an external reset pulse will also initialize the

timing and counter. After either reset is accomplished, the

oscillator frequency is determined by the external RC net-

work. The 16-stage counter divides the oscillator frequency

by any of 4 digitally controlled division ratios.

■ Q/Q select provides output logic level flexibility

■ Reset (auto or master) disables oscillator during reset-

ting to provide no active power dissipation

■ Clock conditioning circuit permits operation with very

slow clock rise and fall times

■ Wide supply voltage range—3.0V to 15V

■ High noise immunity—0.45 V_DD(typ.)

Features

■ Available division ratios 2⁸, 2¹⁰, 2¹³, or 2¹⁶

■ 5V–10V–15V parameter ratings

■ Symmetrical output characteristics

■ Increments on positive edge clock transitions

■ Maximum input leakage 1 µA at 15V over full tempera-

ture range

■ Built-in low power RC oscillator (±2% accuracy over

temperature range and ±10% supply and ±3% over pro-

cessing @ < 10 kHz)

■ High output drive (pin 8) min. one TTL load

Ordering Code:

Order Number Package Number

Package Description

CD4541BCN

N14A

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow

CD4541BCM

M14A

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Pin Assignments for DIP and SOIC

N.C.—Not connected

Top View

DS006001.prf

www.fairchildsemi.com

12 3 4 5 6 7 8

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与CD4541BCM相关器件

型号	品牌	描述	获取价格	数据表
CD4541BCM/A+	TI	IC,TIMER,CMOS,SOP,14PIN,PLASTIC	获取价格
CD4541BCM_NL	FAIRCHILD	暂无描述	获取价格
CD4541BCMX	FAIRCHILD	Analog Timer Circuit	获取价格
CD4541BCMX_NL	FAIRCHILD	Binary Counter, 4000/14000/40000 Series, Asynchronous, Negative Edge Triggered, 14-Bit, Up	获取价格
CD4541BCN	FAIRCHILD	Programmable Timer	获取价格
CD4541BCN	NSC	4000/14000/40000 SERIES, BINARY COUNTER, PDIP14, PLASTIC, DIP-14	获取价格

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