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CD4541BM

更新时间： 2024-11-03 22:40:27
品牌 Logo 应用领域
美国国家半导体 - NSC 触发器逻辑集成电路光电二极管
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6页 140K
描述
Programmable Timer

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CD4541BM 数据手册

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February 1988  
CD4541BM/CD4541BC Programmable Timer  
Y
&
Oscillator frequency range  
DC to 100 kHz  
General Description  
The CD4541B Programmable Timer is designed with  
Y
Y
Y
Y
Oscillator may be bypassed if external clock is available  
(apply external clock to pin 3)  
a
16-stage binary counter, an integrated oscillator for use with  
an external capacitor and two resistors, output control logic,  
and a special power-on reset circuit. The special features of  
the power-on reset circuit are first, no additional static pow-  
er consumption and second, the part functions across the  
full voltage range (3V–15V) whether power-on reset is en-  
abled or disabled.  
Automatic reset initializes all counters when power  
turns on  
External master reset totally independent of automatic  
reset operation  
n
frequency divider or single transition  
Operates at  
timer  
2
Y
Y
Q/Q select provides output logic level flexibility  
Reset (auto or master) disables oscillator during reset-  
ting to provide no active power dissipation  
Clock conditioning circuit permits operation with very  
slow clock rise and fall times  
Timing and the counter are initialized by turning on power, if  
the power-on reset is enabled. When the power is already  
on, an external reset pulse will also initialize the timing and  
counter. After either reset is accomplished, the oscillator  
frequency is determined by the external RC network. The  
16-stage counter divides the oscillator frequency by any of 4  
digitally controlled division ratios.  
Y
Y
Y
Y
Y
Y
Wide supply voltage rangeÐ3.0V to 15V  
High noise immunityÐ0.45 V  
DD  
5V–10V–15V parameter ratings  
(typ.)  
Features  
Symmetrical output characteristics  
Maximum input leakage 1 mA at 15V over full tempera-  
ture range  
8
10 13  
Available division ratios 2 , 2 , 2 , or 2  
16  
Y
Y
Y
Increments on positive edge clock transitions  
Y
g
Built-in low power RC oscillator ( 2% accuracy over  
temperature range and 10% supply and 3% over  
High output drive (pin 8) min. one TTL load  
g
g
@
k
processing  
10 kHz)  
Logic Diagram  
e
V
Pin 7  
SS  
TL/F/6001–1  
Connection Diagram  
Dual-In-Line Package  
Order Number CD4541B  
N.C.ÐNot connected  
TL/F/6001–2  
Top View  
C
1995 National Semiconductor Corporation  
TL/F/6001  
RRD-B30M105/Printed in U. S. A.  
123456

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