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CD4538BCWM PDF预览

CD4538BCWM

更新时间： 2024-11-03 22:39:31
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 预分频器多谐振动器逻辑集成电路光电二极管时钟
页数 文件大小 规格书
11页 137K
描述
Dual Precision Monostable

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中文翻译

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CD4538BCWM 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：SOIC包装说明：SOP, SOP16,.4
针数：16Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：7.74
系列：4000/14000/40000JESD-30 代码：R-PDSO-G16
JESD-609代码：e3长度：9.9 mm
逻辑集成电路类型：MONOSTABLE MULTIVIBRATOR湿度敏感等级：1
数据/时钟输入次数：2功能数量：2
端子数量：16最高工作温度：125 °C
最低工作温度：-55 °C输出极性：COMPLEMENTARY
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP16,.4封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：260
电源：5/15 V传播延迟（tpd）：0.6 ns
认证状态：Not Qualified座面最大高度：1.75 mm
子类别：Prescaler/Multivibrators最大供电电压 (Vsup)：15 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子面层：Matte Tin (Sn)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：3.9 mmBase Number Matches：1

CD4538BCWM 数据手册

 浏览型号CD4538BCWM的Datasheet PDF文件第2页浏览型号CD4538BCWM的Datasheet PDF文件第3页浏览型号CD4538BCWM的Datasheet PDF文件第4页浏览型号CD4538BCWM的Datasheet PDF文件第5页浏览型号CD4538BCWM的Datasheet PDF文件第6页浏览型号CD4538BCWM的Datasheet PDF文件第7页 
October 1987  
Revised January 1999  
CD4538BC  
Dual Precision Monostable  
General Description  
Features  
The CD4538BC is a dual, precision monostable multivibra-  
tor with independent trigger and reset controls. The device  
is retriggerable and resettable, and the control inputs are  
internally latched. Two trigger inputs are provided to allow  
either rising or falling edge triggering. The reset inputs are  
active LOW and prevent triggering while active. Precise  
control of output pulse-width has been achieved using lin-  
ear CMOS techniques. The pulse duration and accuracy  
are determined by external components RX and CX. The  
■ Wide supply voltage range: 3.0V to 15V  
■ High noise immunity: 0.45 VCC (typ.)  
■ Low power TTL compatibility: Fan out of 2 driving 74L  
or 1 driving 74LS  
■ New formula: PWOUT = RC (PW in seconds, R in Ohms,  
C in Farads)  
■ ±1.0% pulse-width variation from part to part (typ.)  
■ Wide pulse-width range: 1 µs to ∞  
■ Separate latched reset inputs  
device does not allow the timing capacitor to discharge  
through the timing pin on power-down condition. For this  
reason, no external protection resistor is required in series  
with the timing pin. Input protection from static discharge is  
provided on all pins.  
■ Symmetrical output sink and source capability  
■ Low standby current: 5 nA (typ.) @ 5 VDC  
■ Pin compatible to CD4528BC  
Ordering Code:  
Order Number Package Number  
Package Description  
CD4538BCM  
CD4538BCWM  
CD4538BCN  
M16A  
M16B  
N16E  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Truth Table  
Pin Assignments for DIP and SOIC  
Inputs  
Outputs  
Clear  
A
X
H
X
L
B
X
X
L
Q
L
L
L
Q
H
H
H
L
X
X
H
H
↓
↑
H
H = HIGH Level  
L = LOW Level  
↑ = Transition from LOW-to-HIGH  
↓ = Transition from HIGH-to-LOW  
= One HIGH Level Pulse  
= One LOW Level Pulse  
X = Irrelevant  
Top View  
© 1999 Fairchild Semiconductor Corporation  
DS006000.prf  
www.fairchildsemi.com  
1234567...11

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