Datasheet > CD4517

CD4517

更新时间： 2024-11-03 00:00:55

品牌	Logo	应用领域
英特矽尔 - INTERSIL		移位寄存器
页数	文件大小	规格书
9页	119K
描述
CMOS Dual 64-Stage Static Shift Register

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中文翻译

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CD4517 数据手册

CD4517BMS

CMOS Dual 64-Stage

Static Shift Register

December 1992

Features

Description

• High-Voltage Types (20-Volt Rating)

• Low Quiescent Current - 10nA/pkg (Typ.) at VDD = 5V

• Clock Frequency 12MHz (Typ.) at VDD = 10V

CD4517BMS dual 64-stage static shift

each having a clock, data, and write enable

input and outputs accessible at taps following

the 16th, 32rd, 48th, and 64th stages. These

taps also serve as input points allowing data

to be inputted at the 17th, 33rd, and 49th

stages when the write enable input is a logic

1 and the clock goes through a low-to-high

transition. The truth table indicates how the

clock and write enable inputs control the

opeation of the CD4517BMS. Inputs at the

intermediate taps allow entry of 64 bits into

the register with 16 clock pulses. The 3-state

outputs permit connection of this device to an

external bus.

• Schmitt Trigger Clock Inputs Allow Operation with Very Slow Clock

Rise and Fall Times

• Capable of Driving Two Low-power TTL Loads, One Low-power

Schottky TTL Load, or Two HTL Loads

• 3-State Outputs

• 100% Tested for Quiescent Current at 20V

• Standardized, Symmetrical Output Characteristics

• 5V, 10V, and 15V Parametric Ratings

• Meets all Requirements of JEDEC Tentative Standard No. 13B,

"Standard Speciﬁcations for Description of ‘B’ Series CMOS

Devices"

The CD4517BMS is supplied in these 16 lead

outline packages:

Braze Seal DIP

Frit Seal DIP

H4X

H1F

Applications

Ceramic Flatpack H6P

• Time-delay Circuits

• Scratch-pad Memories

• General-purpose Serial Shift-register Applications

Pinout

Functional Diagram

CD4517BMS

TOP VIEW

Q16

Q32

Q48

Q64

Q16A

Q48A

WEA

CLA

16 VDD

15 Q16B

14 Q48B

13 WEB

12 CLB

11 Q64B

10 Q32B

D17

D33

D49

16 STAGES

WE = 0

WE = 1

Q64A

Q32A

STAGE 16

OUT/IN TAP

STAGE32

OUT/IN TAP

STAGE 48

OUT/IN TAP

STAGE 64

OUT/IN TAP

VSS

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

File Number 3341

7-1197

12 3 4 5 6 7...9

中文翻译

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与CD4517相关器件

型号	品牌	获取价格	描述	数据表
CD4517B	TI	获取价格	CMOS DUAL 64-STAGE STATIC SHIFT REGISTER
CD4517B	HGSEMI	获取价格	双64位静态移位寄存器
CD4517BD	TI	获取价格	4000/14000/40000 SERIES, 64-BIT RIGHT SERIAL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, CD
CD4517BD	RENESAS	获取价格	IC,SHIFT REGISTER,CMOS,DIP,16PIN,CERAMIC
CD4517BD3	RENESAS	获取价格	Serial In Serial Out, 4000/14000/40000 Series, 64-Bit, Right Direction, True Output, CMOS,
CD4517BDMSH	RENESAS	获取价格	Serial In Serial Out, 4000/14000/40000 Series, 64-Bit, Right Direction, True Output, CMOS,
CD4517BE	TI	获取价格	CMOS Dual 64-Stage Static Shift Register
CD4517BE	ROCHESTER	获取价格	4000/14000/40000 SERIES, 64-BIT RIGHT SERIAL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, PD
CD4517BE	RENESAS	获取价格	IC,SHIFT REGISTER,CMOS,DIP,16PIN,PLASTIC
CD4517BE98	RENESAS	获取价格	CD4517BE98

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