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CD4517BMS PDF预览

CD4517BMS

更新时间: 2024-02-16 06:17:07
品牌 Logo 应用领域
英特矽尔 - INTERSIL 移位寄存器
页数 文件大小 规格书
9页 119K
描述
CMOS Dual 64-Stage Static Shift Register

CD4517BMS 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:DFP, FL16,.3Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.75
其他特性:OUTPUTS ALSO AVAILABLE AT 16TH, 32ND AND 48TH STAGE OF THE SHIFT REGISTER计数方向:RIGHT
系列:4000/14000/40000JESD-30 代码:R-CDFP-F16
JESD-609代码:e0负载电容(CL):50 pF
逻辑集成电路类型:SERIAL IN SERIAL OUT最大频率@ Nom-Sup:3000000 Hz
位数:64功能数量:2
端子数量:16最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:DFP封装等效代码:FL16,.3
封装形状:RECTANGULAR封装形式:FLATPACK
电源:5/15 V传播延迟(tpd):540 ns
认证状态:Not Qualified筛选级别:38535V;38534K;883S
子类别:Shift Registers最大供电电压 (Vsup):18 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:FLAT端子节距:1.27 mm
端子位置:DUAL触发器类型:POSITIVE EDGE
最小 fmax:2.22 MHzBase Number Matches:1

CD4517BMS 数据手册

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CD4517BMS  
CMOS Dual 64-Stage  
Static Shift Register  
December 1992  
Features  
Description  
• High-Voltage Types (20-Volt Rating)  
• Low Quiescent Current - 10nA/pkg (Typ.) at VDD = 5V  
• Clock Frequency 12MHz (Typ.) at VDD = 10V  
CD4517BMS dual 64-stage static shift  
register consists of two independent registers  
each having a clock, data, and write enable  
input and outputs accessible at taps following  
the 16th, 32rd, 48th, and 64th stages. These  
taps also serve as input points allowing data  
to be inputted at the 17th, 33rd, and 49th  
stages when the write enable input is a logic  
1 and the clock goes through a low-to-high  
transition. The truth table indicates how the  
clock and write enable inputs control the  
opeation of the CD4517BMS. Inputs at the  
intermediate taps allow entry of 64 bits into  
the register with 16 clock pulses. The 3-state  
outputs permit connection of this device to an  
external bus.  
• Schmitt Trigger Clock Inputs Allow Operation with Very Slow Clock  
Rise and Fall Times  
• Capable of Driving Two Low-power TTL Loads, One Low-power  
Schottky TTL Load, or Two HTL Loads  
• 3-State Outputs  
• 100% Tested for Quiescent Current at 20V  
• Standardized, Symmetrical Output Characteristics  
• 5V, 10V, and 15V Parametric Ratings  
• Meets all Requirements of JEDEC Tentative Standard No. 13B,  
"Standard Specifications for Description of ‘B’ Series CMOS  
Devices"  
The CD4517BMS is supplied in these 16 lead  
outline packages:  
Braze Seal DIP  
Frit Seal DIP  
H4X  
H1F  
Applications  
Ceramic Flatpack H6P  
• Time-delay Circuits  
• Scratch-pad Memories  
• General-purpose Serial Shift-register Applications  
Pinout  
Functional Diagram  
CD4517BMS  
CL  
TOP VIEW  
CL  
CL  
CL  
CL  
Q16  
Q32  
Q48  
Q64  
Q16A  
Q48A  
WEA  
CLA  
1
2
3
4
5
6
7
8
16 VDD  
15 Q16B  
14 Q48B  
13 WEB  
12 CLB  
11 Q64B  
10 Q32B  
D
D1  
D17  
D33  
D49  
16 STAGES  
16 STAGES  
16 STAGES  
16 STAGES  
WE = 0  
WE = 1  
WE  
Q64A  
Q32A  
DA  
STAGE 16  
OUT/IN TAP  
STAGE32  
OUT/IN TAP  
STAGE 48  
OUT/IN TAP  
STAGE 64  
OUT/IN TAP  
9
DB  
VSS  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
File Number 3341  
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999  
7-1197  

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