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CD4094BCN PDF预览

CD4094BCN

更新时间: 2024-11-03 22:54:19
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 移位寄存器触发器锁存器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
7页 70K
描述
8-Bit Shift Register/Latch with 3-STATE Outputs

CD4094BCN 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP16,.3
针数:16Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.35
其他特性:UNLATCHED SERIAL SHIFT RIGHT OUTPUT; PARALLEL OUTPUT IS LATCHED计数方向:RIGHT
系列:4000/14000/40000JESD-30 代码:R-PDIP-T16
长度:19.305 mm逻辑集成电路类型:SERIAL IN PARALLEL OUT
最大频率@ Nom-Sup:1500000 Hz位数:8
功能数量:1端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5/15 V传播延迟(tpd):840 ns
认证状态:Not Qualified座面最大高度:5.08 mm
子类别:Shift Registers最大供电电压 (Vsup):15 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:7.62 mm最小 fmax:4 MHz
Base Number Matches:1

CD4094BCN 数据手册

 浏览型号CD4094BCN的Datasheet PDF文件第2页浏览型号CD4094BCN的Datasheet PDF文件第3页浏览型号CD4094BCN的Datasheet PDF文件第4页浏览型号CD4094BCN的Datasheet PDF文件第5页浏览型号CD4094BCN的Datasheet PDF文件第6页浏览型号CD4094BCN的Datasheet PDF文件第7页 
October 1987  
Revised January 1999  
CD4094BC  
8-Bit Shift Register/Latch with 3-STATE Outputs  
the latch to 3-STATE output gates. These gates are  
enabled when OUTPUT ENABLE is taken HIGH.  
General Description  
The CD4094BC consists of an 8-bit shift register and a 3-  
STATE 8-bit latch. Data is shifted serially through the shift  
register on the positive transition of the clock. The output of  
the last stage (QS) can be used to cascade several  
Features  
Wide supply voltage range: 3.0V to 18V  
devices. Data on the QS output is transferred to a second  
High noise immunity: 0.45 VDD (typ.)  
output, QS, on the following negative clock edge.  
Low power TTL compatibility:  
Fan out of 2 driving 74L or 1 driving 74LS  
3-STATE outputs  
The output of each stage of the shift register feeds a latch,  
which latches data on the negative edge of the STROBE  
input. When STROBE is HIGH, data propagates through  
Ordering Code:  
Order Number Package Number  
Package Description  
CD4094BCWM  
M16B  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide  
CD4094BCN  
N16E  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Pin Assignments for DIP and SOIC  
Top View  
Truth Table  
Clock  
Output  
Enable  
Strobe  
Data  
Parallel Outputs  
Serial Outputs  
Q1  
QN  
QS  
QΣ  
(Note 1)  
0
0
1
1
1
1
X
X
0
1
1
1
X
X
X
0
1
1
Hi-Z  
Hi-Z  
Hi-Z  
Hi-Z  
Q7  
No Change  
Q7  
No Change  
Q7  
No Change No Change  
No Change  
No Change  
No Change  
Q7  
0
1
QN1  
QN1  
Q7  
Q7  
No Change No Change No Change  
X = Don't Care  
= HIGH-to-LOW  
= LOW-to-HIGH  
Note 1: At the positive clock edge, information in the 7th shift register stage is transferred to Q8 and Q  
.
S
© 1999 Fairchild Semiconductor Corporation  
DS005983.prf  
www.fairchildsemi.com  

CD4094BCN 替代型号

型号 品牌 替代类型 描述 数据表
NLV14094BDR2G ONSEMI

类似代替

8-Stage Shift/Store Register with Three-State Outputs
CD4094BF3A TI

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CMOS 8-Stage Shift-and-Store Nus Register
CD4094BE TI

功能相似

CMOS 8-STAGE SHIFT-AND-STORE BUS REGISTER

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