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CD4094BMS

更新时间: 2024-11-23 22:54:19
品牌 Logo 应用领域
英特矽尔 - INTERSIL /
页数 文件大小 规格书
11页 90K
描述
CMOS 8-Stage Shift-and-Store Bus Register

CD4094BMS 数据手册

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CD4094BMS  
CMOS 8-Stage Shift-and-Store  
Bus Register  
December 1992  
Features  
Pinout  
CD4094BMS  
TOP VIEW  
• High Voltage Type (20V Rating)  
• 3-State Parallel Outputs for Connection to Common  
Bus  
• Separate Serial Outputs Synchronous to Both Positive  
and Negative Clock Edges for Cascading  
STROBE  
DATA  
CLOCK  
Q1  
1
2
3
4
5
6
7
8
16 VDD  
• Medium Speed Operation - 5MHz at 10V (typ)  
• Standardized Symmetrical Output Characteristics  
• 100% Tested for Quiescent Current at 20V  
15 OUTPUT ENABLE  
14 Q5  
13 Q6  
Q2  
12 Q7  
• Maximum Input Current of 1µA at 18V Over Full Pack-  
age Temperature Range; 100nA at 18V and +25oC  
Q3  
11 Q8  
• Noise Margin (Over Full Package/Temperature Range)  
- 1V at VDD = 5V  
10 Q’S  
Q4  
9
QS  
VSS  
- 2V at VDD = 10V  
- 2.5V at VDD = 15V  
• 5V, 10V and 15V Parametric Ratings  
• Meets All Requirements of JEDEC Tentative Standard  
No. 13B, “Standard Specifications for Description of  
‘B’ Series CMOS Devices”  
Functional Diagram  
Applications  
SERIAL  
OUTPUTS  
• Serial-to-Parallel Data Conversion  
• Remote Control Holding Register  
DATA  
2
3
10 Q’S  
8-STAGE  
SHIFT  
CLOCK  
9
QS  
REGISTER  
• Dual-Rank Shift, Hold, and Bus Applications  
Description  
8-BIT  
STORAGE  
REGISTER  
CD4094BMS is a 8-stage serial shift register having a storage  
latch associated with each stage for strobing data from the serial  
input to parallel buffered 3-state outputs. The parallel outputs  
may be connected directly to common bus lines. Data is shifted  
on positive clock transitions. The data in each shift register stage  
is transferred to the storage register when the STROBE input is  
high. Data in the storage register appears at the outputs when-  
ever the OUTPUT-ENABLE signal is high.  
STROBE  
OUTPUT  
1
ENABLE 15  
VDD = 16  
VSS = 8  
3-STATE  
OUTPUTS  
Two serial outputs are available for cascading a number of  
CD4094BMS devices. Data is available at the QS serial output  
terminal on positive clock edges to allow for high-speed opera-  
tion in cascaded systems in which the clock rise time is fast. The  
same serial information, available at the Q’S terminal on the next  
PARALLEL OUTPUTS Q1 - Q8  
(TERMINALS 4, 5, 6, 7, 14, 13, 12, 11, RESPECTIVELY)  
negative clock edge, provides  
a means for cascading  
CD4094BMS devices when the clock rise time is slow.  
The CD4094BMS is supplied in these 16 lead outline packages:  
Braze Seal DIP  
Frit Seal DIP  
H4X  
H1F  
Ceramic Flatpack H6W  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
File Number 3194  
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999  
7-1083  

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