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CD4094BDMSR PDF预览

CD4094BDMSR

更新时间： 2024-11-04 14:48:23
品牌 Logo 应用领域
瑞萨 - RENESAS 输出元件逻辑集成电路触发器
页数 文件大小 规格书
11页 86K
描述
4000/14000/40000 SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, CDIP16, BRAZE SEALED, DIP-16

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CD4094BDMSR 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：DIP包装说明：DIP, DIP16,.3
针数：16Reach Compliance Code：not_compliant
HTS代码：8542.39.00.01风险等级：5.55
计数方向：RIGHT系列：4000/14000/40000
JESD-30 代码：R-CDIP-T16JESD-609代码：e0
逻辑集成电路类型：SERIAL IN PARALLEL OUT最大频率@ Nom-Sup：1250000 Hz
位数：8功能数量：1
端子数量：16最高工作温度：125 °C
最低工作温度：-55 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：CERAMIC, METAL-SEALED COFIRED
封装代码：DIP封装等效代码：DIP16,.3
封装形状：RECTANGULAR封装形式：IN-LINE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5/15 V
传播延迟（tpd）：1134 ns认证状态：Not Qualified
筛选级别：MIL-PRF-38535 Class V座面最大高度：5.08 mm
子类别：Shift Registers标称供电电压 (Vsup)：5 V
表面贴装：NO技术：CMOS
温度等级：MILITARY端子面层：Tin/Lead (Sn/Pb)
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
总剂量：100k Rad(Si) V触发器类型：POSITIVE EDGE
宽度：7.62 mm最小 fmax：0.93 MHz
Base Number Matches：1

CD4094BDMSR 数据手册

 浏览型号CD4094BDMSR的Datasheet PDF文件第2页浏览型号CD4094BDMSR的Datasheet PDF文件第3页浏览型号CD4094BDMSR的Datasheet PDF文件第4页浏览型号CD4094BDMSR的Datasheet PDF文件第5页浏览型号CD4094BDMSR的Datasheet PDF文件第6页浏览型号CD4094BDMSR的Datasheet PDF文件第7页 
CD4094BMS  
CMOS 8-Stage Shift-and-Store  
Bus Register  
December 1992  
Features  
Pinout  
CD4094BMS  
TOP VIEW  
• High Voltage Type (20V Rating)  
• 3-State Parallel Outputs for Connection to Common  
Bus  
• Separate Serial Outputs Synchronous to Both Positive  
and Negative Clock Edges for Cascading  
STROBE  
DATA  
CLOCK  
Q1  
1
2
3
4
5
6
7
8
16 VDD  
• Medium Speed Operation - 5MHz at 10V (typ)  
• Standardized Symmetrical Output Characteristics  
• 100% Tested for Quiescent Current at 20V  
15 OUTPUT ENABLE  
14 Q5  
13 Q6  
Q2  
12 Q7  
• Maximum Input Current of 1µA at 18V Over Full Pack-  
age Temperature Range; 100nA at 18V and +25oC  
Q3  
11 Q8  
• Noise Margin (Over Full Package/Temperature Range)  
- 1V at VDD = 5V  
10 Q’S  
Q4  
9
QS  
VSS  
- 2V at VDD = 10V  
- 2.5V at VDD = 15V  
• 5V, 10V and 15V Parametric Ratings  
• Meets All Requirements of JEDEC Tentative Standard  
No. 13B, “Standard Specifications for Description of  
‘B’ Series CMOS Devices”  
Functional Diagram  
Applications  
SERIAL  
OUTPUTS  
• Serial-to-Parallel Data Conversion  
• Remote Control Holding Register  
DATA  
2
3
10 Q’S  
8-STAGE  
SHIFT  
CLOCK  
9
QS  
REGISTER  
• Dual-Rank Shift, Hold, and Bus Applications  
Description  
8-BIT  
STORAGE  
REGISTER  
CD4094BMS is a 8-stage serial shift register having a storage  
latch associated with each stage for strobing data from the serial  
input to parallel buffered 3-state outputs. The parallel outputs  
may be connected directly to common bus lines. Data is shifted  
on positive clock transitions. The data in each shift register stage  
is transferred to the storage register when the STROBE input is  
high. Data in the storage register appears at the outputs when-  
ever the OUTPUT-ENABLE signal is high.  
STROBE  
OUTPUT  
1
ENABLE 15  
VDD = 16  
VSS = 8  
3-STATE  
OUTPUTS  
Two serial outputs are available for cascading a number of  
CD4094BMS devices. Data is available at the QS serial output  
terminal on positive clock edges to allow for high-speed opera-  
tion in cascaded systems in which the clock rise time is fast. The  
same serial information, available at the Q’S terminal on the next  
PARALLEL OUTPUTS Q1 - Q8  
(TERMINALS 4, 5, 6, 7, 14, 13, 12, 11, RESPECTIVELY)  
negative clock edge, provides  
a means for cascading  
CD4094BMS devices when the clock rise time is slow.  
The CD4094BMS is supplied in these 16 lead outline packages:  
Braze Seal DIP  
Frit Seal DIP  
H4X  
H1F  
Ceramic Flatpack H6W  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
File Number 3194  
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999  
7-1083  
1234567...11

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