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CD4094 PDF预览

CD4094

更新时间: 2024-09-30 22:54:19
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 移位寄存器锁存器
页数 文件大小 规格书
7页 70K
描述
8-Bit Shift Register/Latch with 3-STATE Outputs

CD4094 数据手册

 浏览型号CD4094的Datasheet PDF文件第2页浏览型号CD4094的Datasheet PDF文件第3页浏览型号CD4094的Datasheet PDF文件第4页浏览型号CD4094的Datasheet PDF文件第5页浏览型号CD4094的Datasheet PDF文件第6页浏览型号CD4094的Datasheet PDF文件第7页 
October 1987  
Revised January 1999  
CD4094BC  
8-Bit Shift Register/Latch with 3-STATE Outputs  
the latch to 3-STATE output gates. These gates are  
enabled when OUTPUT ENABLE is taken HIGH.  
General Description  
The CD4094BC consists of an 8-bit shift register and a 3-  
STATE 8-bit latch. Data is shifted serially through the shift  
register on the positive transition of the clock. The output of  
the last stage (QS) can be used to cascade several  
Features  
Wide supply voltage range: 3.0V to 18V  
devices. Data on the QS output is transferred to a second  
High noise immunity: 0.45 VDD (typ.)  
output, QS, on the following negative clock edge.  
Low power TTL compatibility:  
Fan out of 2 driving 74L or 1 driving 74LS  
3-STATE outputs  
The output of each stage of the shift register feeds a latch,  
which latches data on the negative edge of the STROBE  
input. When STROBE is HIGH, data propagates through  
Ordering Code:  
Order Number Package Number  
Package Description  
CD4094BCWM  
M16B  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide  
CD4094BCN  
N16E  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Pin Assignments for DIP and SOIC  
Top View  
Truth Table  
Clock  
Output  
Enable  
Strobe  
Data  
Parallel Outputs  
Serial Outputs  
Q1  
QN  
QS  
QΣ  
(Note 1)  
0
0
1
1
1
1
X
X
0
1
1
1
X
X
X
0
1
1
Hi-Z  
Hi-Z  
Hi-Z  
Hi-Z  
Q7  
No Change  
Q7  
No Change  
Q7  
No Change No Change  
No Change  
No Change  
No Change  
Q7  
0
1
QN1  
QN1  
Q7  
Q7  
No Change No Change No Change  
X = Don't Care  
= HIGH-to-LOW  
= LOW-to-HIGH  
Note 1: At the positive clock edge, information in the 7th shift register stage is transferred to Q8 and Q  
.
S
© 1999 Fairchild Semiconductor Corporation  
DS005983.prf  
www.fairchildsemi.com  

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