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CD4073BDMSR PDF预览

CD4073BDMSR

更新时间: 2024-11-04 14:29:31
品牌 Logo 应用领域
瑞萨 - RENESAS 输入元件逻辑集成电路触发器
页数 文件大小 规格书
10页 114K
描述
4000/14000/40000 SERIES, TRIPLE 3-INPUT AND GATE, CDIP14

CD4073BDMSR 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP14,.3
针数:14Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.22
系列:4000/14000/40000JESD-30 代码:R-CDIP-T14
JESD-609代码:e0长度:9.585 mm
负载电容(CL):50 pF逻辑集成电路类型:AND GATE
最大I(ol):0.00036 A功能数量:3
输入次数:3端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:DIP
封装等效代码:DIP14,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5/15 VProp。Delay @ Nom-Sup:338 ns
传播延迟(tpd):338 ns认证状态:Not Qualified
施密特触发器:NO筛选级别:MIL-PRF-38535 Class V
座面最大高度:5.33 mm子类别:Gates
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED总剂量:100k Rad(Si) V
宽度:7.62 mmBase Number Matches:1

CD4073BDMSR 数据手册

 浏览型号CD4073BDMSR的Datasheet PDF文件第2页浏览型号CD4073BDMSR的Datasheet PDF文件第3页浏览型号CD4073BDMSR的Datasheet PDF文件第4页浏览型号CD4073BDMSR的Datasheet PDF文件第5页浏览型号CD4073BDMSR的Datasheet PDF文件第6页浏览型号CD4073BDMSR的Datasheet PDF文件第7页 
CD4073BMS, CD4081BMS  
CD4082BMS  
CMOS AND Gate  
January 1993  
Features  
Pinout  
CD4073BMS  
TOP VIEW  
• High-Voltage Types (20V Rating)  
• CD4073BMS Triple 3-Input AND Gate  
• CD4081BMS Quad 2-Input AND Gate  
• CD4082BMS Dual 4-Input AND Gate  
A
1
2
3
4
5
6
7
14 VDD  
B
13  
12  
11  
G
H
I
• Medium Speed Operation:  
D
- tPLH, tPHL = 60ns (typ) at VDD = 10V  
E
• 100% Tested for Quiescent Current at 20V  
F
K = D E F  
VSS  
10 L = G H I  
• Maximum Input Current of 1µA at 18V Over Full Pack-  
age Temperature Range; 100nA at 18V and +25oC  
9
8
J = A B C  
C
• Noise Margin (Over Full Package Temperature Range):  
- 1V at VDD = 5V  
- 2V at VDD = 10V  
CD4081BMS  
TOP VIEW  
- 2.5V at VDD = 15V  
• Standardized Symmetrical Output Characteristics  
• 5V, 10V and 15V Parametric Ratings  
A
1
2
3
4
5
6
7
14 VDD  
• Meets All Requirements of JEDEC Tentative Standard  
No. 13B, “Standard Specifications for Description of  
‘B’ Series CMOS Devices”  
B
J = A B  
K = C D  
C
13  
12  
H
G
11 M = G H  
10 L = E F  
Description  
CD4073BMS, CD4081BMS and CD4082BMS AND gates  
provide the system designer with direct implementation of  
the AND function and supplement the existing family of  
CMOS gates.  
D
9
8
F
E
VSS  
The CD4073BMS, CD4081BMS and CD4082BMS are supplied  
in these 14 lead outline packages:  
CD4082BMS  
TOP VIEW  
Braze Seal DIP  
Frit Seal DIP  
*H4Q †H4H  
*H1B  
J = A B C D  
1
2
3
4
5
6
7
14 VDD  
D
C
13 K = E F G H  
Ceramic Flatpack  
*H3W  
12  
11  
10  
9
H
*CD4073B, CD4081B †CD4082B  
B
G
F
A
NC  
VSS  
E
8
NC  
NC = NO CONNECTION  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
File Number 3324  
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999  
7-433  

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