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CD4066BDMS PDF预览

CD4066BDMS

更新时间: 2024-11-20 15:29:19
品牌 Logo 应用领域
瑞萨 - RENESAS /
页数 文件大小 规格书
9页 99K
描述
QUAD 1-CHANNEL, SGL POLE SGL THROW SWITCH, CDIP14, BRAZE SEALED, DIP-14

CD4066BDMS 技术参数

生命周期:Obsolete零件包装代码:DIP
包装说明:DIP,针数:14
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.58模拟集成电路 - 其他类型:SPST
JESD-30 代码:R-CDIP-T14JESD-609代码:e0
标称负供电电压 (Vsup):信道数量:1
功能数量:4端子数量:14
最大通态电阻 (Ron):1300 Ω最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:DIP封装形状:RECTANGULAR
封装形式:IN-LINE认证状态:Not Qualified
筛选级别:MIL-PRF-38535 Class V座面最大高度:5.08 mm
标称供电电压 (Vsup):5 V表面贴装:NO
最长断开时间:70 ns最长接通时间:70 ns
技术:CMOS温度等级:MILITARY
端子面层:TIN LEAD端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
宽度:7.62 mmBase Number Matches:1

CD4066BDMS 数据手册

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CD4066BMS  
CMOS Quad Bilateral Switch  
December 1992  
Features  
Description  
• For Transmission or Multiplexing of Analog or Digital CD4066BMS is a quad bilateral switch intended for the  
Signals  
transmission or multiplexing of analog or digital signals. It is  
pin for pin compatible with CD4016B, but exhibits a much  
lower on state resistance. In addition, the on-state resistance  
is relatively constant over the full input signal range.  
• High Voltage Types (20V Rating)  
• 15V Digital or ±7.5V Peak-to-Peak Switching  
• 125Typical On-State Resistance for 15V Operation  
The CD4066BMS consists of four independent bilateral  
switches. A single control signal is required per switch. Both  
the p and the n device in a given switch are biased on or off  
simultaneously by the control signal. As shown in Figure 1,  
the well of the n channel device on each switch is either tied  
to the input when the switch is on or to VSS when the switch  
is off. This configuration eliminates the variation of the switch  
transistor threshold voltage with input signal, and thus keeps  
the on-state resistance low over the full operating signal  
range.  
• Switch On-State Resistance Matched to Within 5Ω  
Over 15V Signal Input Range  
• On-State Resistance Flat Over Full Peak-to-Peak Sig-  
nal Range  
• High On/Off Output Voltage Ratio  
- 80dB Typ. at FIS = 10kHz, RL = 1kΩ  
• High Degree of Linearity: <0.5% Distortion Typ. at  
FIS = 1kHz, VIS = 5Vp-p, VDD - VSS 10V, RL = 10kΩ  
The advantages over single channel switches include peak  
input signal voltage swings equal to the full supply voltage,  
and more constant on-state impedance over the input signal  
range. For sample and hold applications, however, the  
CD4016B is recommended.  
• Extremely Low Off-State Switch Leakage Resulting in  
Very Low Offset Current and High Effective Off-State  
Resistance: 10pA Typ. at VDD - VSS = 10V, TA = +25oC  
• Extremely High Control Input Impedance (Control Cir-  
The CD4066BMS is supplied in these 14-lead outline pack-  
ages:  
cuit Isolated from Signal Circuit): 1012Typ.  
• Low Crosstalk Between Switches: -50dB Typ. at FIS =  
8MHz, RL = 1kΩ  
Braze Seal DIP  
Frit Seal DIP  
H4Q  
H1B  
• Matched  
Control  
Input  
to  
Signal  
Output  
Ceramic Flatpack H3W  
Capacitance: Reduces Output Signal Transients  
• Frequency Response, Switch on = 40MHz (Typ.)  
• 100% Tested for Quiescent Current at 20V  
• 5V, 10V and 15V Parametric Ratings  
Pinout  
CD4066BMS  
TOP VIEW  
• Meets All Requirements of JEDEC Tentative Standard  
No. 13B, “Standard Specifications for Description of  
“B” Series CMOS Devices”  
IN/OUT A  
OUT/IN A  
OUT/IN B  
IN/OUT B  
CONT B  
CONT C  
VSS  
1
2
3
4
5
6
7
14 VDD  
13 CONT A  
12 CONT D  
11 IN/OUT D  
10 OUT/IN D  
Applications  
• Analog Signal Switching/Multiplexing  
- Signal Gating  
- Squelch Control  
- Chopper  
- Modulator  
- Demodulator  
9
8
OUT/IN C  
IN/OUT C  
- Commutating Switch  
• Digital Signal Switching/Multiplexing  
• Transmission Gate Logic Implementation  
• Analog to Digital & Digital to Analog Conversion  
• Digital Control of Frequency, Impedance, Phase, and  
Analog Signal Gain  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
File Number 3319  
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999  
7-966  

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