ꢀꢁꢂ ꢃ ꢄ ꢅ ꢆꢇꢈ ꢅ ꢉ ꢀꢁꢂ ꢃ ꢄ ꢊ ꢆꢇꢈ ꢅ ꢉ ꢀꢁ ꢂꢃ ꢄꢋ ꢆꢇ ꢈ ꢅ
ꢀꢌ ꢍ ꢎ ꢏꢐꢏ ꢑꢍ ꢒ ꢌ ꢓꢑꢔ ꢕꢖ ꢑꢗ ꢘꢗꢙꢎ ꢚꢁꢗ ꢌꢓ ꢑꢔ ꢕꢖ ꢑꢗ ꢘꢗ ꢙ ꢎ
ꢛ ꢕꢔ ꢜ ꢑ ꢍꢒ ꢕ ꢀꢝꢑ ꢗꢞꢗ ꢑ ꢀꢍ ꢐꢞ ꢗꢙ ꢎ ꢕꢍ ꢐ
SCHS354 − AUGUST 2004
D
D
Matched Switching Characteristics,
= 5 Ω (Typ) for V − V = 15 V
Features
r
on
DD
EE
D
Qualification in Accordance With
AEC-Q100
Very Low Quiescent Power Dissipation
Under All Digital-Control Input and Supply
Conditions, 0.2 µW (Typ)
†
D
Qualified for Automotive Applications
D
Customer-Specific Configuration Control
Can Be Supported Along With
Major-Change Approval
at V
− V = V
− V = 10 V
DD
SS
DD EE
D
D
D
D
Binary Address Decoding on Chip
5-V, 10-V, and 15-V Parametric Ratings
100% Tested for Quiescent Current at 20 V
D
D
Wide Range of Digital and Analog Signal
Levels
− Digital: 3 V to 20 V
Maximum Input Current of 1µA at 18 V Over
Full Package Temperature Range, 100 nA at
18 V and 25°C
Break-Before-Make Switching Eliminates
Channel Overlap
− Analog: 3 20 V
P-P
Low ON Resistance, 125 Ω (Typ) Over
15 V Signal Input Range
D
P-P
for V
− V = 18 V
DD
EE
D
D
High OFF Resistance, Channel Leakage of
+ 100 pA (Typ) at V − V = 18 V
Applications
DD
EE
Logic-Level Conversion for Digital
Addressing Signals of 3 V to 20 V
D
Analog and Digital Multiplexing and
Demultiplexing
(V
− V = 3 V to 20 V) to Switch Analog
DD
SS
D
D
Analog-to-Digital (A/D) and
Digital-to-Analog (D/A) Conversion
Signals to 20 V
(V
− V = 20 V)
P-P DD EE
†
Contact factory for details. Q100 qualification data available on
request.
Signal Gating
description/ordering information
The CD4051B, CD4052B, and CD4053B analog multiplexers are digitally-controlled analog switches that have
low ON impedance and very low OFF leakage current. Control of analog signals up to 20 V can be achieved
P-P
by digital signal amplitudes of 4.5 V to 20 V (If V
− V = 3 V, a V
− V of up to 13 V can be controlled;
DD
SS
DD EE
for V
− V
level differences above 13 V, a V
− V
of at least 4.5 V is required). For example, if
= 4.5 V, V = 0 V, and V = −13.5 V, analog signals from −13.5 V to 4.5 V can be controlled by digital
inputs of 0 V to 5 V. These multiplexer circuits dissipate extremely low quiescent power over the full V
DD
EE
DD
SS
V
DD
SS EE
− V
SS
DD
and V
− V supply-voltage ranges, independent of the logic state of the control signals. When a logic high
DD
EE
(H) is present at the inhibit (INH) input, all channels are off.
ORDERING INFORMATION
ORDERABLE
TOP-SIDE
MARKING
‡
PACKAGE
T
A
PART NUMBER
CD4051BQM96Q1
CD4051BQPWRQ1
SOIC − M
Reel of 2500
Reel of 2000
Reel of 2500
Reel of 2000
Reel of 2500
Reel of 2000
CD4051Q
TSSOP − PW
SOIC − M
CM051BQ
CD4052Q
CD4052Q
CD4053Q
CD4053Q
§
CD4052BQM96Q1
−40°C to 125°C
§
TSSOP − PW
SOIC − M
CD4052BQPWRQ1
CD4053BQM96Q1
CD4053BQPWRQ1
§
TSSOP − PW
‡
§
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Product Preview
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2004, Texas Instruments Incorporated
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