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CD4052BQM96Q1 PDF预览

CD4052BQM96Q1

更新时间: 2024-11-19 22:25:15
品牌 Logo 应用领域
德州仪器 - TI 解复用器开关复用器或开关信号电路光电二极管
页数 文件大小 规格书
18页 394K
描述
CMOS ALALOG MULTIPLEXERS/DEMULTIPLEXERS WITH LOGIC-LEVEL CONVERSION

CD4052BQM96Q1 技术参数

生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP, SOP16,.25针数:16
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.6Is Samacsys:N
模拟集成电路 - 其他类型:DIFFERENTIAL MULTIPLEXERJESD-30 代码:R-PDSO-G16
长度:9.9 mm负电源电压最大值(Vsup):-10 V
负电源电压最小值(Vsup):-2.5 V标称负供电电压 (Vsup):-5 V
信道数量:4功能数量:1
端子数量:16通态电阻匹配规范:15 Ω
最大通态电阻 (Ron):1050 Ω最高工作温度:125 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
电源:5/15 V认证状态:Not Qualified
座面最大高度:1.75 mm最大信号电流:0.01 A
子类别:Multiplexer or Switches最大供电电流 (Isup):0.6 mA
最大供电电压 (Vsup):10 V最小供电电压 (Vsup):2.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
最长断开时间:720 ns最长接通时间:720 ns
切换:BREAK-BEFORE-MAKE技术:CMOS
温度等级:AUTOMOTIVE端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
宽度:3.9 mmBase Number Matches:1

CD4052BQM96Q1 数据手册

 浏览型号CD4052BQM96Q1的Datasheet PDF文件第2页浏览型号CD4052BQM96Q1的Datasheet PDF文件第3页浏览型号CD4052BQM96Q1的Datasheet PDF文件第4页浏览型号CD4052BQM96Q1的Datasheet PDF文件第5页浏览型号CD4052BQM96Q1的Datasheet PDF文件第6页浏览型号CD4052BQM96Q1的Datasheet PDF文件第7页 
ꢀꢁꢂ ꢃ ꢄ ꢅ ꢆꢇꢈ ꢅ ꢉ ꢀꢁꢂ ꢃ ꢄ ꢊ ꢆꢇꢈ ꢅ ꢉ ꢀꢁ ꢂꢃ ꢄꢋ ꢆꢇ ꢈ ꢅ  
ꢀꢌ ꢍ ꢎ ꢏꢐꢏ ꢑꢍ ꢒ ꢌ ꢓꢑꢔ ꢕꢖ ꢑꢗ ꢘꢗꢙꢎ ꢚꢁꢗ ꢌꢓ ꢑꢔ ꢕꢖ ꢑꢗ ꢘꢗ ꢙ ꢎ  
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SCHS354 − AUGUST 2004  
D
D
Matched Switching Characteristics,  
= 5 (Typ) for V − V = 15 V  
Features  
r
on  
DD  
EE  
D
Qualification in Accordance With  
AEC-Q100  
Very Low Quiescent Power Dissipation  
Under All Digital-Control Input and Supply  
Conditions, 0.2 µW (Typ)  
D
Qualified for Automotive Applications  
D
Customer-Specific Configuration Control  
Can Be Supported Along With  
Major-Change Approval  
at V  
− V = V  
− V = 10 V  
DD  
SS  
DD EE  
D
D
D
D
Binary Address Decoding on Chip  
5-V, 10-V, and 15-V Parametric Ratings  
100% Tested for Quiescent Current at 20 V  
D
D
Wide Range of Digital and Analog Signal  
Levels  
− Digital: 3 V to 20 V  
Maximum Input Current of 1µA at 18 V Over  
Full Package Temperature Range, 100 nA at  
18 V and 25°C  
Break-Before-Make Switching Eliminates  
Channel Overlap  
− Analog: 3 20 V  
P-P  
Low ON Resistance, 125 (Typ) Over  
15 V Signal Input Range  
D
P-P  
for V  
− V = 18 V  
DD  
EE  
D
D
High OFF Resistance, Channel Leakage of  
+ 100 pA (Typ) at V − V = 18 V  
Applications  
DD  
EE  
Logic-Level Conversion for Digital  
Addressing Signals of 3 V to 20 V  
D
Analog and Digital Multiplexing and  
Demultiplexing  
(V  
− V = 3 V to 20 V) to Switch Analog  
DD  
SS  
D
D
Analog-to-Digital (A/D) and  
Digital-to-Analog (D/A) Conversion  
Signals to 20 V  
(V  
− V = 20 V)  
P-P DD EE  
Contact factory for details. Q100 qualification data available on  
request.  
Signal Gating  
description/ordering information  
The CD4051B, CD4052B, and CD4053B analog multiplexers are digitally-controlled analog switches that have  
low ON impedance and very low OFF leakage current. Control of analog signals up to 20 V can be achieved  
P-P  
by digital signal amplitudes of 4.5 V to 20 V (If V  
− V = 3 V, a V  
− V of up to 13 V can be controlled;  
DD  
SS  
DD EE  
for V  
− V  
level differences above 13 V, a V  
− V  
of at least 4.5 V is required). For example, if  
= 4.5 V, V = 0 V, and V = −13.5 V, analog signals from −13.5 V to 4.5 V can be controlled by digital  
inputs of 0 V to 5 V. These multiplexer circuits dissipate extremely low quiescent power over the full V  
DD  
EE  
DD  
SS  
V
DD  
SS EE  
− V  
SS  
DD  
and V  
− V supply-voltage ranges, independent of the logic state of the control signals. When a logic high  
DD  
EE  
(H) is present at the inhibit (INH) input, all channels are off.  
ORDERING INFORMATION  
ORDERABLE  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
PART NUMBER  
CD4051BQM96Q1  
CD4051BQPWRQ1  
SOIC − M  
Reel of 2500  
Reel of 2000  
Reel of 2500  
Reel of 2000  
Reel of 2500  
Reel of 2000  
CD4051Q  
TSSOP − PW  
SOIC − M  
CM051BQ  
CD4052Q  
CD4052Q  
CD4053Q  
CD4053Q  
§
CD4052BQM96Q1  
−40°C to 125°C  
§
TSSOP − PW  
SOIC − M  
CD4052BQPWRQ1  
CD4053BQM96Q1  
CD4053BQPWRQ1  
§
TSSOP − PW  
§
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Product Preview  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2004, Texas Instruments Incorporated  
ꢓ ꢐ ꢑꢗꢎꢎ ꢍ ꢔꢜ ꢗꢙꢛ ꢕꢎ ꢗ ꢐ ꢍꢔꢗꢁ ꢟꢠ ꢡꢢ ꢣꢤꢥ ꢦꢧꢨ ꢩꢟ ꢥꢤ ꢩꢟꢪ ꢡꢩꢢ ꢖꢙ ꢍ ꢁ ꢓ ꢀꢔ ꢕꢍ ꢐ  
ꢭꢪ ꢬ ꢪ ꢧ ꢨ ꢟ ꢨ ꢬ ꢢ ꢰ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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