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CD4027BC PDF预览

CD4027BC

更新时间: 2024-09-15 22:54:19
品牌 Logo 应用领域
美国国家半导体 - NSC 触发器
页数 文件大小 规格书
6页 128K
描述
Dual J-K Master/Slave Flip-Flop with Set and Reset

CD4027BC 数据手册

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February 1988  
CD4027BM/CD4027BC Dual J-K Master/Slave  
Flip-Flop with Set and Reset  
General Description  
Features  
Y
Wide supply voltage range  
3.0V to 15V  
0.45 V (typ.)  
These dual J-K flip-flops are monolithic complementary  
MOS (CMOS) integrated circuits constructed with N- and P-  
channel enhancement mode transistors. Each flip-flop has  
independent J, K, set, reset, and clock inputs and buffered  
Q and Q outputs. These flip-flops are edge sensitive to the  
clock input and change state on the positive-going transition  
of the clock pulses. Set or reset is independent of the clock  
and is accomplished by a high level on the respective input.  
Y
High noise immunity  
DD  
Y
Low power TTL  
compatibility  
Fan out of 2 driving 74L  
or 1 driving 74LS  
50 nW (typ.)  
Y
Low power  
Y
Medium speed operation  
12 MHz (typ.)  
with 10V supply  
All inputs are protected against damage due to static dis-  
.
SS  
charge by diode clamps to V  
and V  
DD  
Schematic and Connection Diagrams  
TL/F/5958–1  
Dual-In-Line Package  
Order Number CD4027B  
TL/F/5958–2  
Top View  
C
1995 National Semiconductor Corporation  
TL/F/5958  
RRD-B30M105/Printed in U. S. A.  

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