Datasheet > CD4021BMS

CD4021BMS

更新时间： 2024-11-03 22:54:19

品牌	Logo	应用领域
英特矽尔 - INTERSIL		移位寄存器逻辑集成电路
页数	文件大小	规格书
9页	96K
描述
CMOS 8-Stage Static Shift Registers

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中文翻译

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数据手册

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CD4021BMS 数据手册

CD4014BMS,

CD4021BMS

CMOS 8-Stage Static Shift Registers

December 1992

Features

Description

• High Voltage Types (20V Rating)

CD4014BMS -Synchronous Parallel or Serial Input/Serial Output

• Medium Speed Operation 12MHz (Typ.) Clock Rate at CD4021BMS -Asynchronous Parallel Input or Synchronous

VDD-VSS = 10V

Serial Input/Serial Output

• Fully Static Operation

CD4014BMS and CD4021BMS series types are 8-stage paral-

lel- or serial-input/serial output registers having common CLOCK

and PARALLEL/SERIAL CONTROL inputs, a single SERIAL

data input, and individual parallel “JAM” inputs to each register

stage. Each register stage is a D-type, master-slave ﬂip-ﬂop. In

addition to an output from stage 8, “Q” outputs are also available

from stages 6 and 7. Parallel as well as serial entry is made into

the register synchronously with the positive clock line transition in

the CD4014BMS. In the CD4021BMS serial entry is synchro-

nous with the clock but parallel entry is asynchronous. In both

types, entry is controlled by the PARALLEL/SERIAL CONTROL

input. When the PARALLEL/SERIAL CONTROL input is low,

data is serially shifted into the 8-stage register synchronously

with the positive transition of the clock line. When the PARALLEL/

SERIAL CONTROL input is high, data is jammed into the 8-

stage register via the parallel input lines and synchronous with

the positive transition of the clock line. In the CD4021BMS, the

CLOCK input of the internal stage is “forced” when asynchro-

nous parallel entry is made. Register expansion using multiple

packages is permitted.

• 8 Master-Slave Flip-Flops Plus Output Buffering and

Control Gating

• 100% Tested for Quiescent Current at 20V

• Maximum Input Current of 1µA at 18V Over Full Pack-

age Temperature Range; 100nA at 18V and +25^oC

• Noise Margin (Full Package Temperature Range)

• 1V at VDD = 5V

• 2V at VDD = 10V

• 2.5V at VDD = 15V

• Standardized Symmetrical Output Characteristics

• 5V, 10V and 15V Parametric Ratings

• Meets All Requirements of JEDEC Tentative Standard

No. 13B, “Standard Speciﬁcations for Description of

`B' Series CMOS Devices

The CD4014BMS and CD4021BMS are supplied in these 16

lead outline packages:

Applications:

• Parallel Input/Serial Output Data Queueing

• Parallel to Serial Data Conversion

• General Purpose Register

Braze Seal DIP

Frit Seal DIP

H4T

H1F

Ceramic Flatpack H6W

Pinout

Functional Diagram

PAR. IN

VDD

PI-8

16 VDD

2 3 4 5 6 7 8

15 PI-7

4 13 14 15 1

14 PI-6

PI-4

PI-3

PI-2

PI-1

VSS

13 PI-5

PARALLEL/SERIAL

CONTROL

12 Q7

11 SERIAL IN

10 CLOCK

SERIAL IN

CLOCK

PARALLEL/SERIAL

CONTROL

VSS

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

File Number 3294

7-80

12 3 4 5 6 7...9

中文翻译

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与CD4021BMS相关器件

型号	品牌	获取价格	描述	数据表
CD4021BMT	TI	获取价格	CMOS 8-Stage Static Shift Registers
CD4021BMTE4	TI	获取价格	CMOS 8-Stage Statice Shift Registers
CD4021BMTG4	TI	获取价格	CMOS 8-Stage Statice Shift Registers
CD4021BMW	NSC	获取价格	IC,SHIFT REGISTER,CMOS,FP,16PIN,CERAMIC
CD4021BMW/883	NSC	获取价格	IC,SHIFT REGISTER,CMOS,FP,16PIN,CERAMIC
CD4021BMW/883B	NSC	获取价格	IC,SHIFT REGISTER,CMOS,FP,16PIN,CERAMIC
CD4021BNSR	TI	获取价格	CMOS 8-Stage Static Shift Registers
CD4021BNSRE4	TI	获取价格	4000/14000/40000 SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, P
CD4021BPW	TI	获取价格	CMOS 8-Stage Static Shift Registers
CD4021BPWE4	TI	获取价格	CMOS 8-Stage Statice Shift Registers

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