CD4021B-Q1
www.ti.com
SCHS378 –MARCH 2010
CMOS 8-STAGE STATIC SHIFT REGISTER
Check for Samples: CD4021B-Q1
1
FEATURES
•
Qualified for Automotive Applications
•
•
Meets All Requirements of JEDEC Tentative
Standard No. 13B, "Standard Specifications for
Description of 'B' Series CMOS Devices"
•
Medium-Speed Operation: 12-MHz (Typ) Clock
Rate at VDD – VSS = 10 V
Latch-Up Performance Meets 50 mA per JESD
78, Class I
•
•
Fully Static Operation
Eight Master-Slave Flip-Flops Plus Output
Buffering and Control Gating
APPLICATIONS
•
•
100% Tested for Quiescent Current at 20 V
•
•
•
Parallel Input/Serial Output Data Queuing
Parallel-to-Serial Data Conversion
General-Purpose Register
Maximum Input Current of 1 µA at 18 V Over
Full Package-Temperature Range:
100 nA at 18 V and 25°C
•
Noise Margin (Full Package-Temperature
Range):
D PACKAGE
(TOP VIEW)
–
–
–
1 V at VDD = 5 V
2 V at VDD = 10 V
2.5 V at VDD = 15 V
•
•
Standardized Symmetrical Output
Characteristics
5-V, 10-V, and 15-V Parametric Ratings
DESCRIPTION
CD4021B series types are 8-stage parallel- or serial-input/serial output registers having common CLOCK and
PARALLEL/SERIAL CONTROL inputs, a single SERIAL data input, and individual parallel "JAM" inputs to each
register stage. Each register stage is a D-type, master-slave flip-flop. In addition to an output from stage 8, "Q"
outputs are also available from stages 6 and 7. Parallel as well as serial entry is made into the register
synchronously with the positive clock line transition in the CD4014B. In the CD4021B serial entry is synchronous
with the clock but parallel entry is asynchronous. In both types, entry is controlled by the PARALLEL/SERIAL
CONTROL input. When the PARALLEL/SERIAL CONTROL input is low, data is serially shifted into the 8-stage
register synchronously with the positive transition of the clock line. When the PARALLEL/SERIAL CONTROL
input is high, data is jammed into the 8-stage register via the parallel input lines and synchronous with the
positive transition of the clock line. In the CD4021B, the CLOCK input of the internal stage is "forced" when
asynchronous parallel entry is made. Register expansion using multiple packages is permitted.
The CD4021B series types are supplied in 16-lead hermetic dual-in-line ceramic packages (D and F suffixes),
16-lead dual-in-line plastic packages (E suffix), and in chip form (H suffix).
ORDERING INFORMATION(1)
TA
PACKAGE(2)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
CD4021BQ
–40°C to 125°C
SOIC – D
Reel of 2500
CD4010BQDRQ1
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
5秒后页面跳转
SG3525资料手册详解：SG3525参数分析、引脚说明、应用介绍
AT89C51单片机资料手册详细解析及应用示例
CP2102资料手册解读：CP2102引脚说明、关键参数分析
资料手册解读：UC3842参数和管脚说明
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
