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CD4022BCJ PDF预览

CD4022BCJ

更新时间: 2024-11-05 22:54:19
品牌 Logo 应用领域
美国国家半导体 - NSC 计数器触发器逻辑集成电路输出元件
页数 文件大小 规格书
8页 168K
描述
Decade Counter/Divider with 10 Decoded Outputs, Divide-by-8 Counter/Divider with 8 Decoded Outputs

CD4022BCJ 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP16,.3Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.64
其他特性:JOHNSON COUNTER WITH 8 DECODED OUTPUTS; TCO OUTPUT; GATED CLOCK计数方向:UP
系列:4000/14000/40000JESD-30 代码:R-GDIP-T16
JESD-609代码:e0长度:19.43 mm
负载电容(CL):50 pF负载/预设输入:NO
逻辑集成电路类型:RING COUNTER最大频率@ Nom-Sup:1000000 Hz
工作模式:SYNCHRONOUS位数:8
功能数量:1端子数量:16
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:3/15 V传播延迟(tpd):1000 ns
认证状态:Not Qualified座面最大高度:5.08 mm
子类别:Counters最大供电电压 (Vsup):15 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:7.62 mm
最小 fmax:1 MHzBase Number Matches:1

CD4022BCJ 数据手册

 浏览型号CD4022BCJ的Datasheet PDF文件第2页浏览型号CD4022BCJ的Datasheet PDF文件第3页浏览型号CD4022BCJ的Datasheet PDF文件第4页浏览型号CD4022BCJ的Datasheet PDF文件第5页浏览型号CD4022BCJ的Datasheet PDF文件第6页浏览型号CD4022BCJ的Datasheet PDF文件第7页 
March 1988  
CD4017BM/CD4017BC Decade Counter/Divider  
with 10 Decoded Outputs  
CD4022BM/CD4022BC Divide-by-8 Counter/Divider  
with 8 Decoded Outputs  
General Description  
The CD4017BM/CD4017BC is a 5-stage divide-by-10 John-  
son counter with 10 decoded outputs and a carry out bit.  
Features  
Y
Wide supply voltage range  
3.0V to 15V  
0.45 V (typ.)  
Y
High noise immunity  
DD  
Y
Low power  
TTL compatibility  
Fan out of 2 driving 74L  
or 1 driving 74LS  
The CD4022BM/CD4022BC is a 4-stage divide-by-8 John-  
son counter with 8 decoded outputs and a carry-out bit.  
Y
Medium speed operation  
5.0 MHz (typ.)  
with 10V V  
DD  
These counters are cleared to their zero count by a logical  
‘‘1’’ on their reset line. These counters are advanced on the  
positive edge of the clock signal when the clock enable sig-  
nal is in the logical ‘‘0’’ state.  
Y
Low power  
10 mW (typ.)  
Y
Fully static operation  
The configuration of the CD4017BM/CD4017BC and  
CD4022BM/CD4022BC permits medium speed operation  
and assures a hazard free counting sequence. The 10/8  
decoded outputs are normally in the logical ‘‘0’’ state and go  
to the logical ‘‘1’’ state only at their respective time slot.  
Each decoded output remains high for 1 full clock cycle.  
The carry-out signal completes a full cycle for every 10/8  
clock input cycles and is used as a ripple carry signal to any  
succeeding stages.  
Applications  
Y
Automotive  
Y
Instrumentation  
Y
Medical electronics  
Y
Alarm systems  
Y
Industrial electronics  
Y
Remote metering  
Connection Diagrams  
CD4017B  
Dual-In-Line Package  
CD4022B  
Dual-In-Line Package  
TL/F/5950–1  
TL/F/5950–2  
Top View  
Top View  
Order Number CD4017B or CD4022B  
C
1995 National Semiconductor Corporation  
TL/F/5950  
RRD-B30M105/Printed in U. S. A.  

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IC,COUNTER,UP,MODULO-8,CMOS,DIP,16PIN,CERAMIC