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CD4011BDMSR PDF预览

CD4011BDMSR

更新时间: 2024-02-01 08:46:07
品牌 Logo 应用领域
瑞萨 - RENESAS 输入元件逻辑集成电路触发器
页数 文件大小 规格书
9页 110K
描述
4000/14000/40000 SERIES, QUAD 2-INPUT NAND GATE, CDIP14

CD4011BDMSR 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP14,.3
针数:14Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.64
系列:4000/14000/40000JESD-30 代码:R-CDIP-T14
JESD-609代码:e0长度:19.43 mm
负载电容(CL):50 pF逻辑集成电路类型:NAND GATE
最大I(ol):0.00036 A功能数量:4
输入次数:2端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:DIP
封装等效代码:DIP14,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5/15 VProp。Delay @ Nom-Sup:338 ns
传播延迟(tpd):338 ns认证状态:Not Qualified
施密特触发器:NO筛选级别:MIL-PRF-38535 Class V
座面最大高度:1 mm子类别:Gates
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:0.5 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED总剂量:100k Rad(Si) V
宽度:2 mmBase Number Matches:1

CD4011BDMSR 数据手册

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CD4011BMS, CD4012BMS  
CD4023BMS  
CMOS NAND Gates  
November 1994  
Features  
Pinouts  
CD4011BMS  
TOP VIEW  
• High-Voltage Types (20V Rating)  
• Propagation Delay Time = 60ns (typ.) at CL = 50pF,  
VDD = 10V  
A
B
1
2
3
4
5
6
7
14 VDD  
• Buffered Inputs and Outputs  
13  
12  
H
G
• Standardized Symmetrical Output Characteristics  
J = AB  
K = CD  
C
• Maximum Input Current of 1µA at 18V Over Full Package-  
11 M = GH  
10 L = EF  
Temperature Range; 100nA at 18V and +25oC  
• 100% Tested for Maximum Quiescent Current at 20V  
• 5V, 10V and 15V Parametric Ratings  
D
9
8
E
F
VSS  
• Noise Margin (Over Full Package Temperature Range):  
- 1V at VDD = 5V  
CD4012BMS  
TOP VIEW  
- 2V at VDD = 10V  
- 2.5V at VDD = 15V  
• Meets All Requirements of JEDEC Tentative Stan-  
dards No. 13B, “Standard Specifications for Descrip-  
tion of “B” Series CMOS Device’s  
J = ABCD  
1
2
3
4
5
6
7
14 VDD  
A
B
13 K = EFGH  
12  
11  
10  
9
H
Description  
C
G
F
CD4011BMS - Quad 2 Input  
CD4012BMS - Dual 4 Input  
CD4023BMS - Triple 3 Input  
D
NC  
VSS  
E
8
NC  
NC = NO CONNECTION  
CD4011BMS, CD4012BMS, and CD4023BMS NAND gates  
provide the system designer with direct implementation of  
the NAND function and supplement the existing family of  
CMOS gates. All inputs and outputs are buffered.  
CD4023BMS  
TOP VIEW  
The CD4011BMS, CD4012BMS and the CD4023BMS is  
supplied in these 14 lead outline packages:  
A
1
2
3
4
5
6
7
14 VDD  
B
13  
12  
11  
G
H
I
CD4011B  
H4Q  
CD4012B  
H4H  
CD4023B  
H4Q  
D
Braze Seal DIP  
Frit Seal DIP  
E
F
H1B  
H1B  
H1B  
10 L = GHI  
H3W  
H3W  
H3W  
K = DEF  
VSS  
9
8
J = ABC  
C
Ceramic Flatpack  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
File Number 3079  
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999  
7-53  

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