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CD40106BFMSR PDF预览

CD40106BFMSR

更新时间: 2024-09-14 14:05:51
品牌 Logo 应用领域
瑞萨 - RENESAS 输入元件逻辑集成电路触发器
页数 文件大小 规格书
9页 77K
描述
HEX 1-INPUT INVERT GATE, CDIP14, FRIT SEALED, DIP-14

CD40106BFMSR 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP14,.3
针数:14Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.16
JESD-30 代码:R-GDIP-T14JESD-609代码:e0
长度:9.585 mm负载电容(CL):50 pF
逻辑集成电路类型:INVERTER最大I(ol):0.00036 A
功能数量:6输入次数:1
端子数量:14最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DIP封装等效代码:DIP14,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5/15 V
Prop。Delay @ Nom-Sup:378 ns传播延迟(tpd):378 ns
认证状态:Not Qualified施密特触发器:YES
筛选级别:MIL-PRF-38535 Class V座面最大高度:5.33 mm
子类别:Gates标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
总剂量:100k Rad(Si) V宽度:7.62 mm
Base Number Matches:1

CD40106BFMSR 数据手册

 浏览型号CD40106BFMSR的Datasheet PDF文件第2页浏览型号CD40106BFMSR的Datasheet PDF文件第3页浏览型号CD40106BFMSR的Datasheet PDF文件第4页浏览型号CD40106BFMSR的Datasheet PDF文件第5页浏览型号CD40106BFMSR的Datasheet PDF文件第6页浏览型号CD40106BFMSR的Datasheet PDF文件第7页 
CD40106BMS  
CMOS Hex Schmitt Triggers  
December 1992  
Features  
Pinout  
CD40106BMS  
TOP VIEW  
• High Voltage Type (20V Rating)  
• Schmitt Trigger Action with No External Components  
• Hysteresis Voltage (Typ.)  
- 0.9V at VDD = 5V  
A
G = A  
B
1
2
3
4
5
6
7
14 VDD  
13 F  
-
2.3V at VDD = 10V  
12 L = F  
11 E  
- 3.5V at VDD = 15V  
H = B  
C
• Noise Immunity Greater than 50%  
• No Limit on Input Rise and Fall Times  
• Low VDD to VSS Current During Slow Input Ramp  
• 100% Tested for Quiescent Current at 20V  
• 5V, 10V and 15V Parametric Ratings  
10 K = E  
I = C  
VSS  
9
8
D
J = D  
• Maximum Input Current of 1µA at 18V Over Full Pack- Functional Diagram  
age Temperature Range; 100nA at 18V and +25oC  
1
2
4
• Standardized Symmetrical Output Characteristics  
A
G = A  
H = B  
I = C  
• Meets All Requirements of JEDEC Tentative Standard  
No. 13B, “Standard Specifications for Description of  
‘B’ Series CMOS Devices”  
3
5
B
C
D
E
F
6
Applications  
• Wave and Pulse Shapers  
• High Noise Environment Systems  
• Monostable Multivibrators  
• Astable Multivibrators  
9
8
J = D  
K = E  
L = F  
11  
13  
10  
12  
Description  
CD40106BMS consists of six Schmitt trigger circuits. Each  
circuit functions as an inverter with Schmitt trigger action on  
the input. The trigger switches at different points for positive  
and negative going signals. The difference between the  
positive going voltage (VP) and the negative going voltage  
(VN) is defined as hysteresis voltage (VH) (see Figure 17).  
Logic Diagram  
*
*
A
G
1 (3, 5, 9, 11, 13)  
2 (4, 6, 8, 10, 12)  
The CD40106BMS is supplied in these 14 lead outline  
packages:  
VDD  
Braze Seal DIP  
Frit Seal DIP  
H4Q  
H1B  
H3W  
ALL INPUTS ARE PROTECTED  
BY CMOS PROTECTION  
NETWORK  
*
Ceramic Flatpack  
VSS  
FIGURE 1. 1 OF 6 SCHMITT TRIGGERS  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
File Number 3354  
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999  
7-1327  

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