CAT28F102
Licensed Intel
second source
1 Megabit CMOS Flash Memory
FEATURES
■ 64K x 16 Word Organization
■ Fast Read Access Time: 100/120 ns
■ Stop Timer for Program/Erase
■ Low Power CMOS Dissipation:
–Active: 30 mA max (CMOS/TTL levels)
–Standby: 1 mA max (TTL levels)
–Standby: 100 µA max (CMOS levels)
■ On-Chip Address and Data Latches
■ JEDEC Standard Pinouts:
–40-pin DIP
■ High Speed Programming:
–10 µs per byte
–44-pin PLCC
–40-pin TSOP
–1 Sec Typ Chip Program
■ 100,000 Program/Erase Cycles
■ 10 Year Data Retention
■ Electronic Signature
■ 0.5 Seconds Typical Chip-Erase
■ 12.0V ± 5% Programming and Erase Voltage
■ Commercial,Industrial and Automotive
Temperature Ranges
DESCRIPTION
write cycle scheme. Address and Data are latched to
free the I/O bus and address bus during the write
operation.
TheCAT28F102isahighspeed64Kx16-bitelectrically
erasable and reprogrammable Flash memory ideally
suited for applications requiring in-system or after-sale
code updates. Electrical erasure of the full memory
contents is achieved typically within 0.5 second.
The CAT28F102 is manufactured using Catalyst’s
advancedCMOSfloatinggatetechnology.Itisdesigned
to endure 100,000 program/erase cycles and has a data
retention of 10 years. The device is available in JEDEC
approved 40-pin DIP, 44-pin PLCC, or 40-pin TSOP
packages.
It is pin and Read timing compatible with standard
EPROMandE2PROMdevices.ProgrammingandErase
areperformedthroughanoperationandverifyalgorithm.
The instructions are input via the I/O bus, using a two
I/O –I/O
BLOCK DIAGRAM
0
15
I/O BUFFERS
ERASE VOLTAGE
SWITCH
WE
DATA
LATCH
SENSE
AMP
COMMAND
REGISTER
PROGRAM VOLTAGE
SWITCH
CE, OE LOGIC
CE
OE
Y-GATING
Y-DECODER
1,048,576-BIT
MEMORY
ARRAY
A –A
15
0
X-DECODER
VOLTAGE VERIFY
SWITCH
Doc. No. 1014, Rev. A
© 2001 by Catalyst Semiconductor, Inc.
1
Characteristics subject to change without notice